Sony DSR-1 Service Manual page 127

CXD2189AR-T6 (SONY)
C-MOS CHANNEL ENCODER/DECODER(FOR DIGITAL VCR)
–TOP VIEW–
76
77
78 V
DD(+3V)
GND
79
80
81
82
83
84
85
86
87
88 GND
89
90
91
92
93
94
95
96
97
98
99
100
RECON
78
REC CK
4
DRCK REF
3
PD OUT
DRCK
98
VCO IN
97 PLL
VCO OUT
100
DRCK OUT
RECMD
DUB
68-75
IDGEN
REC DATA7-0
80
IDPG
TR PLS
79
FR PLS TMG
PAL
GEN
PF
HD
67
AFTER REC TIMG
66
SYNC PLS
54-61
PB DATA7 - 0
64
AV DATA EN
65
SUB-CODE EN
43
ERROR PLS
62
PB CK
PBON
85
RST
81
SERIAL IN
82
SERIAL OUT MECH COM
83
CLOCK
I/F
SSA
84
CS
DSR-1/1P/V2
50
49
48
47
46
45
44
43
42
41
40
39
GND 38
37
36
35
34
33
32
31
30
GND
29
V
DD(+3V) 28
27
26
RECON RMZON APT/TP/PF TSG (1 : 0)
REC CK
GEN
TEST GEN
ITI GEN
SUB-CODE
PTG PILOT DET
CODE
PILOT ERR
GEN
8 8 8
V/A
RMZ
PTG RUN LENGTH CHECK
AFREC REF
AFREC REF GEN
TIMING CNT
APLI ID DET
V/A C1 ECC
ID ERR
ERR CNT ID CORRECT
CHK
SYN CNT
SUBCODE
ECC
BIST P
IED5ON
IECON
APT/ITP/PF
CLEC (2 : 0)
ERCNT
INPUT
4 3
DRCK REF PD OUT
AZIMUTH
97
98
VCO IN VCO OUT
CK (13.5M)
68 100
REC DATA7 DRCK OUT
CLOCK
69 89
REC DATA6 P-SAVE0
CS
70 90
REC DATA5 P-SAVE1
DO PLS
71 8
REC DATA4 REC DATA CK
DRCK REF
6
72
REC DATA3 REC DATA
FR PLS
73 7
REC DATA2 REC
PBDT0 - 6
74 93
REC DATA1 REC2
PB CK IN
75 78
REC DATA0 REC CK
RST
79
FR PLS
SERIAL IN
96
80
TR PLS CLK DLY
SUB-CODE
87 92
SUB-CODE TAPE MODE
TEST SEL0, 1
44 94
PBDT0 PLL-SEARCH
TR PLS
45 95
PBDT1 PLL F-RUN
VCO IN
46 67
PBDT2 AFTER REC TIMG
54
47
PBDT3 PB DATA 7
OUTPUT
48 55
PBDT4 PB DATA 6
AFTER REC TIMG
49 56
PBDT5 PB DATA 5
AV DATA EN
50 57
PBDT6 PB DATA 4
CLK DLY
86 58
AZIMUTH PB DATA 3
DRCK OUT
59
53
PB CK IN PB DATA 2
EYE CK
60
91
PB DATA 1
EYE DATA 0- 6
DO PLS
61
PB DATA 0
ERROR PLS
66
SYNC PLS
PB ADJ CK
5 65
CK(13.5M) SUB-CODE EN
PB CK OUT
64
AV DATA EN
PB DATA 0 - 7
43
ERROR PLS PD OUT
62 PLL F-RUN
PB CK OUT
PLL-SEARCH
81 82
SERIAL IN SERIAL OUT
P-SAVE0, 1
34
83
CLOCK EYE DATA 0
REC
84 35
CS EYE DATA 1 REC2
36
EYE DATA 2
REC CK
37
EYE DATA 3 REC DATA
39
EYE DATA 4
REC DATA 0 - 7
40
EYE DATA 5 REC DATA CK
41
EYE DATA 6 SERIAL OUT
33
EYE CK SUB CODE EN
42
PB ADJ CK SYNC PLS
43
ERROR PLS TAPE MODE
32
9
TEST SEL0 PB TEST VCO OUT
10 11
TEST SEL1 TEST0
12
TEST1 INPUT/OUTPUT
14
TEST2 PB TEST
15
TEST3
16
TEST4
17
TEST5
18
TEST6
28
TEST7
29
TEST8
30
TEST9
31
TEST10
RST
85
TSGON BISTR (15 : 0)
BIST R
CODE
SEL
MUX
P/S
2
S/P
8 &
SYNC
SEL
DET
STATE
DRMZ
MACHINE
& FW
BUF
DRMZON PTST VITION
VIT (6 : 0)
FSTION
32
; AZIMUTH ID SIGNAL
; 13.5MHz PLL ADJUSTING CLOCK
; MICROCOMPUTER CLOCK INPUT
; MICROCOMPUTER CHIP SELECT
; DROPOUT PULSE
; DRCK CLOCK REFERENCE
; FRAME PULSE
; PLAYBACK DATA
; PLAYBACK CLOCK INPUT
; SYSTEM RESET (L = RESET)
; MICROCOMPUTER SERIAL DATA INPUT
; SUB-CODE AREA SIGNAL
; TEST SIGNAL MODE
; TRACK PULSE
; DRCK PLL OSCILLATOR INPUT
; AFTER RECORDING TIMING
; AUDIO/VIDEO DATA ENABLE PERIOD (H = ENABLE)
; DRCK CLOCK DELAY ROUGH ADJUSTMENT
; DRCK PLL OUTPUT
; EYE-PATTERN CHECK CLOCK (TEST DATA)
; EYE-PATTERN CHECK DATA (TEST DATA)
; ERROR PULSE
; 1/25 PLAYBACK CLOCK (FOR ADJUSTMENT)
; PLAYBACK CLOCK OUTPUT
; PLAYBACK DATA
; DRCK PLL PHASE DETECT
; PLL FREE-RUN MODE
; PLL HIGH-SPEED SEARCH MODE
; POWER SAVE (P-SAVE0 = EVEN CH, P-SAVE1 = ODD CH)
; RECORDING PERIOD
; RECORDING PERIOD
; RECORDING SYSTEM CLOCK (5MHz)
; RECORDING DATA
; RECORDING DATA
; CLOCK (41.85MHz) FOR RECORDING DATA
; MICROCOMPUTER SERIAL DATA OUTPUT
; SUB-CODE ENABLE PERIOD (H = ENABLE)
; SYNC PULSE
; EQ MP TAPE MODE
; DRCK PLL OSCILLATOR OUTPUT
; TEST SIGNAL I/O FOR PLAYBACK SYSTEM
5
PIAJ (10 : 0)
PLL F0
ADJ
89,90
RFPS P-SAVE0,1
8
REC DATA CK
6
REC DATA
7 REC
93 REC2
87
SUB-CODE
16
VIT 1-D 2 44-50
PBDT0 -PBDT6
86
AZIMUTH
GPAJ
PBCK 53
PBCK
GEN
FOLON PBON
96
BNMON
CLK DLY
91
DO PLS
GPA (15 : 0) 92
TAPE MODE
95
GPB (15 : 0)
PLL F-RUN
94
34-37
PLL SEARCH
39-41 33 42
IC
14-13