Power-On Sequence And System Reset; Power-On Sequence; Reset; Flash (Compulsory) And Sram (Optional) - Espressif Systems ESP32-S2 Hardware Design Manuallines

2. Schematic Checklist
2.2 Power­on Sequence and System Reset
2.2.1 Power­on Sequence
ESP32-S2 uses a 3.3 V system power supply. The chip should be activated after the power rails have stabilized.
This is achieved by delaying the activation of CHIP_PU after the 3.3 V rails have been brought up. More details
can be found in Section Power Scheme in
Notice:
To ensure the power supply to the ESP32-S2 chip during power-up, it is advised to add an RC delay circuit at the
CHIP_PU pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 µF. However,
specific parameters should be adjusted based on the power-up timing of the power supply and the power-up and
reset sequence timing of the chip.

2.2.2 Reset

CHIP_PU serves as the reset pin of ESP32-S2. The reset voltage (V
fied in Section DC Characteristics in
the CHIP_PU trace as short as possible, and add a pull-up resistor as well as a capacitor to the ground whenever
possible.
Notice:
CHIP_PU pin must not be left floating.

2.3 Flash (compulsory) and SRAM (optional)

ESP32-S2 can support up to 1 GB external flash and 1 GB external SRAM. The ESP32-S2-WROVER module
uses a 4 MB SPI flash and 2 MB PSRAM, powered by VDD_SPI. Make sure to select the appropriate flash and
PSRAM according to the power voltage on VDD_SPI. We recommend reserving a serial resistor (a 0 Ω resistor
can be used initially) on the SPI communication line, to lower the driving current, reduce interference to RF, adjust
timing, and improve anti-interference ability.
The schematic for ESP32-S2 flash and SRAM is shown in Figure 4.
Espressif Systems
ESP32-S2 Datasheet.
ESP32-S2 Datasheet. To avoid reboots caused by external interferences, route
5
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) should meet the requirements speci-
IL_nRST
ESP32-S2 Hardware Design Guidelines V1.1