Espressif Systems ESP32-S2 Hardware Design Manuallines page 18

3. PCB Layout Design
3.5 RF
In a four-layer PCB design, the RF trace is routed as shown highlighted in pink in Figure 15.
• The RF trace should have 50 Ω single-ended characteristic impedance. The reference plane is the second
layer. A π-type matching circuitry should be reserved on the RF trace and placed close to the chip.
• Make sure to keep the width of the RF trace consistent, and do not branch the trace. The RF trace should
be as short as possible with dense ground via stitching around it for isolation.
• The RF trace should be routed on the outer layer without vias, i.e., should not cross layers. The RF trace
should be routed at a 135° angle, or with circular arcs if trace bends are required.
• The ground plane on the adjacent layer needs to be complete. Do not route any traces under the RF trace
whenever possible.
• There should be no high-frequency signal traces routed close to the RF trace. The RF antenna should be
placed away from high-frequency transmitting devices, such as crystal oscillators, DDR, and clocks, etc.
In addition, the USB port, USB-to-UART chip, UART signal lines (including traces, vias, test points, header
pins, etc.) must be as far away from the antenna as possible. It is good practice to add ground vias around
the UART signal line.
• When doing 50 Ω single-ended impedance control for the RF trace, please refer to the PCB stack-up design
shown in Figure 16.
Espressif Systems
Figure 14: ESP32­S2 Crystal Oscillator Layout
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ESP32-S2 Hardware Design Guidelines V1.1