Pcb Layout Guidelines - Analog Devices EVAL-SSM2311 Manual

PCB LAYOUT GUIDELINES

To keep the EMI under the allowable limit and to ensure that
the amplifier chip operates under the temperature limit, PCB
layout is critical in application designs. Figure 3 shows the
preferred layout for the SSM2311.
GO TO VSS PLANE
BY VIA
GO TO VDD PLANE BY VIA
Figure 3. Preferred PCB Layout for SSM2311
VIA SIZE SHOULD BE
AS LARGE AS POSSIBLE
GO TO VSS PLANE BY VIA
Rev. 0 | Page 5 of 12
Layer Stacks and Grounding
The stack-up for the evaluation board is a 4-layer structure.

Top layer—component layer with power and output copper
land and ground copper pouring.

nd
2 layer—dedicated ground plane.

rd
3 layer—dedicated power plane.

Bottom layer—bottom layer with ground copper pouring.
Components Placement and Clearance
Place all related components except decoupling capacitors on
the same side as the SSM2311 and as close as possible to the
chip to avoid vias (see Figure 5).
Place decoupling capacitors on the bottom side and close to the
GND pin (see Figure 7).
Top Layer Copper Land and Ground Pouring
The output peak current of this amplifier is more than 1 A, so
PCB traces should be wide (>2 mm) to handle the high current.
For the best performance, use symmetrical copper lands as large
as space allows, instead of traces for the output pins (see Figure 3).
Pour ground copper on the top side and use many vias to connect
the top layer ground copper to the dedicated ground plane. The
copper pouring on the top layer serves as both the EMI shielding
ground plane and the heat sink for the SSM2311.
The SSM2311 works well only if these techniques are implemented
in the PCB design to keep EMI and the amplifier temperature low.
EVAL-SSM2311