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A
33V
33V
22K
22K
R5
R6
VT
C3
C4
C5
D
0.22uF/50V
0.22uF/50V
100pF
BM
Q2
Q3
Q4
2SA1015
2SA1015
2SA1015
BL
C
BH
BU
TEST3AB
TEST3AB
S1
S2
220
220
R31
R32
B
330
560
R33
R34
2.2K
R40
1
6
2
5
S3
3
4
TS1565W0-V50C
A
A
B
VCC1
470pF
C1
R1
22K
R2
10K
4.7K
10K
R9
R10
Q1
PH2369
R11
C6
33K
100pF
R14
R12
R13
33K
33K
33K
R17
R16
R15
L/R
U/D
4.5MHz
CN1
CN2
1
1
2
2
STB
PH-2
PH-2
820
R35
R37
1K
B
C
R3
10K
U2
1
EEP SCL
VJC SCL
2
VT
EEP SDA
3
R VOL
VCJ SDA
4
L VOL
MONITOR
R25
22K
5
REAR VIEW
H SYNC
6
SECAM L
V SYNC
22K
7
VL
B
22K
8
VH
G
22K
9
U
R
R18
1K
10
KEY
BLANK
R19
1K
11
L/R
CLK CONT
R20
1K
12
U/D
AV1
R21
22K
13
4.5MHz OUT
AV2
14
A MUTE
50/60 OUT
15
ASPE1
FSC IN
16
ASPE2
RESET
17
POWER
S-VHS IN
18
GND
FACTORY ADJ
19
GND
IR IN
20
NC
FILT
21
Vcc
Vcc
M37160
VDD
VDD
C11
100uF/16V
C
D
24C08N-10SC
U1
R4
8
1
C2
Vcc
A0
10K
0.01uF
7
2
WP
A1
6
3
SCL
A2
5
4
SDA
GND
42
41
40
39
38
37
36
35
34
33
32
31
30
R23
1K
29
28
R26
100
27
C7
R28
10K
26
0.01uF
R30
10K
25
24
C8
23
100pF
22
C9
C10
470pF
0.01uF
R36
22K
0.01uF
R38
+
C12
1K
AKAI AFT-505
DATE
SHEET
APPROVED
CHECK DESIGN
D
E
VCC1
VCC1
R7
R8
10K
10K
D
SCL
SDA
MON
HD
VD
B
G
R
C
BLANK
CLK
50/60
FSC
RESET
R29
22K
B
U3
1
OUT
100
2
GND
R39
3
Vcc
PIC-1018SMD
+
C13
47uF/6.3V
A
TITLE
CPU
OF
1
4
SCHEMATIC DIAGRAM
DRAW
DRAWING NO.
ZD2.025.0 55DL
E
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