Aim APE429-32 Hardware Manual
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Aim APE429-32 Hardware Manual

32 channels arinc429 test & simulation module for pci express
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APE429-32
32 Channels
ARINC429 Test & Simulation Module
For PCI Express
APE429-32 Hardware Manual
Hardware
Manual
V01.00 Rev. A
July 2016
i

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Summary of Contents for Aim APE429-32

  • Page 1 APE429-32 32 Channels ARINC429 Test & Simulation Module For PCI Express Hardware Manual V01.00 Rev. A July 2016 APE429-32 Hardware Manual...
  • Page 3 APE429-32 32-Channels ARINC429 Test & Simulation Module for PCI Express Hardware Manual V01.00 Rev. A July 2016 AIM No: 60-121B6-16-0100-A APE429-32 Hardware Manual...
  • Page 4 Notice: The information that is provided in this document is believed to be accurate. No responsibility is assumed by AIM GmbH for its use. No license or rights are granted by implication in connection therewith. Specifications are subject to change without notice.
  • Page 5 DOCUMENT HISTORY The following table defines the history of this document. Appendix A provides a more comprehensive list of changes made with each version. Version Cover Date Created by Description V01.00 Rev. A 12.07.2016 S.Thota First Released Version APE429-32 Hardware Manual...
  • Page 6 THIS PAGE INTENTIONALLY LEFT BLANK APE429-32 Hardware Manual...

  • Page 7: Table Of Contents

    Preparation and Precaution for Installation ................9 Installation Instructions ......................9 Connecting to other Devices ....................10 2.3.1 APE429-32 Front panel Connector Pinout ................11 Front Panel LEDs ........................12 Structure of the APE429-32 ................. 13 PCI-Express bus and BIU-I/O FPGA ..................14 3.1.1...
  • Page 8 Page Figure 2-1: Front Panel view ..................10 Figure 2-2: Status LED view ..................12 Figure 3-1: Block Diagram of APE429-32 ..............13 Figure 3-2 : IRIG Jumper ....................17 Figure 3-3 : 16-pin Ribbon Cable Connector ..............18 Figure 3-4 : Ribbon Cable / Cable connection ............... 19...

  • Page 9: Introduction

    For programming information please refer to the documents listed in the 'Applicable Documents' section. The APE429-32 is a member of AIM’s new family of advanced PCI-Express module for analysis, simulation, monitoring and testing of ARINC429 channels providing 32 channels. The PCI-Express Interface is 1-lane wide and working with 2.5 Gbit/s in transmits and receive direction.

  • Page 10: How This Manual Is Organized

    Section 3 - STRUCTURE OF THE APE429-32 - Describes the physical hardware interfaces on the APE429-32 using a block diagram and a description of each main component Section 4 - TECHNICAL DATA - describes the technical specification of the APE429-32.

  • Page 11: Installation

    4. Find a free PCIe slot in your system. 5. Remove the slot bracket from the slot you have chosen and put it aside. 6. Align the APE429-32 card slot connector with the PCIe slot and gently lower the card into the free slot.

  • Page 12: Connecting To Other Devices

    The connection to other devices is done via a SCSI-3 female connector. The Front panel have 32 ARINC429 channels, IRIG IN/OUT and Trigger OUT. The APE429-32 implementation has the capability to share the I/O- pins. This means each ARINC429 channel can be used as Transmit or Receive channel, but only one operation mode is possible at one time.

  • Page 13: Ape429-32 Front Panel Connector Pinout

    Installation 2.3.1 APE429-32 Front panel Connector Pinout 68 pin SCSI-3 female connector, Downward Compatibility Mode Signal Direction Pin No. Signal Direction Type Type TxRx_True_1 Bidir. TxRx_Comp_1 Bidir. TxRx_True_2 Bidir. TxRx_Comp_2 Bidir. TxRx_True_3 Bidir. TxRx_Comp_3 Bidir. TxRx_True_4 Bidir. TxRx_Comp_4 Bidir. TxRx_True_5 Bidir.

  • Page 14: Front Panel Leds

    LED illuminates if an error during the BIU self-test occurs. RX-ERR LED flashes if an error on any channel is detected. RX-ERR- LED illuminates if an error on any channel is detected LATCH (stored error). Table 2-2: Front Panel LED description APE429-32 Hardware Manual...

  • Page 15: Structure Of The Ape429-32

    Structure of the APE429-32 3 STRUCTURE OF THE APE429-32 The structure of the APE429-32 is shown in Figure 3-1. This card comprises the following main sections:  PCI Express bus and BIU-IO FPGA  Global RAM  BIU Processors Section (2-BIU’s) ...

  • Page 16: Pci-Express Bus And Biu-I/O Fpga

    Structure of the APE429-32 3.1 PCI-Express bus and BIU-I/O FPGA The new common FPGA architecture of AIM’s PCI-Express family includes a complete PCI-Express bus logic (which is translated to a legacy PCI interface using an external bridge component) and the 2-BIU processors logic. This programmable device implements the following features: ...

  • Page 17: Arinc-429 Encoder

    (if no special transmission mode is chosen) 3.6 External Trigger Output One Trigger output is provided on APE429-32 variant. The Trigger output is TTL level compatible. Filter circuitry is provided at the trigger output to cover Electromagnetic Compatibility (EMC) aspects.

  • Page 18: Time Code Encoder/Decoder

    The generated time code signal is an IRIG-B compatible sinusoidal waveform. The time code information can be used for time-tagging and multi-channel synchronization. On the APE429-32 a new generation IRIG-B section is implemented with a free-wheeling IRIG functionality. If no external IRIG signal is detected, the TCP switches automatically to the free-wheeling mode.

  • Page 19: Board To Board (B2B) Connector As Irig In/Out

    Structure of the APE429-32 3.7.3 Board to Board (B2B) connector as IRIG In/Out Normally for connecting the IRIG Input and/or Output the 68 pin SCSI-3 female connector is used for wiring. Follow the instructions below if the B2B connector is used instead.

  • Page 20: Board To Board Connector (B2B Connector)

    Structure of the APE429-32 3.8 Board to Board Connector (B2B connector) The Board to Board connector provides an additional one pin combined IRIG-B Master- Output/Slave Input on a 16-pin ribbon cable connector (mounted on the upper right corner, see figure 3.13-1).

  • Page 21: General Purpose Discrete Inputs/Outputs (Gpio)

    If there is a requirement to provide the B2B connector signals externally (outside the PC), an optional AIM Breakout-Panel, which occupies one PC-Slot, can be used to get out the signals. Please ask for a Breakout Panel if there is a request.
  • Page 22 Structure of the APE429-32 THIS PAGE INTENTIONALLY LEFT BLANK APE429-32 Hardware Manual...

  • Page 23: Technical Data

    Measurement of gap between two labels in the range from 0.0 to 58.75 bits with 0.25bit resolution. Error detection capabilities:  Gap Error Detection  Bit count Error Detection  Coding Error Detection  Parity Error Detection (if no special transmission mode is chosen) APE429-32 Hardware Manual...
  • Page 24 Transmitter channel Output Impedance 75 Ω Channel 1-32 are fixed output amplitude of typically ± 10 V High / Low Speed: Rise and fall time automatically switched via Analogue Switches to meet the requirement for High / Low Speed operation APE429-32 Hardware Manual...
  • Page 25 (3) Low Speed (LS2) 12, 5 kHz; worst case load (400 Ohm || 30 nF); 100 % Duty Cycle Temperature: Standard Operating +50°C Extended Temperature (on request) +60°C Storage +85°C Humidity: 0% to 95% non-condensing Weight: ~ 200g for the APE429-32 APE429-32 Hardware Manual...
  • Page 26 Technical data THIS PAGE INTENTIONALLY LEFT BLANK APE429-32 Hardware Manual...

  • Page 27: Notes

    Random Access Memory SIMM Single Inline Memory Module SRAM Static Random Access Memory SSRAM Synchronous Static Random Access Memory SDRAM Synchronous Dynamic RAM Software Test Access Port (for JTAG) Time Code Processor UART Universal Asynchronous Receiver and Transmitter APE429-32 Hardware Manual...
  • Page 28 Notes THIS PAGE INTENTIONALLY LEFT BLANK APE429-32 Hardware Manual...

  • Page 29: Certificate Of Volatility

    Erase Personalization Media Does the item contain media storage capability (i.e., removable or non-removable disk drives, tape drives, memory cards, etc.)? Description of used media storage: Type: Size: User Modifiable: Function: Process to Sanitize: -None- Additional Information: APE429-32 Hardware Manual...
  • Page 30 All operating Data for handling the I/O Protocol will be stored in volatile memory only. No Transfer data is stored in Non-Volatile Memory. The Non-Volatile Memory only contains production relevant data for board personalization, FPGA Logic or Firmware Code for the on board Microcontroller. APE429-32 Hardware Manual...

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