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Summary of Contents for PLX Technology USB3382-AIC Rapid
- Page 1 USB3382-AIC RDK PLX Technology Hardware Reference Manual USB3382-AIC Rapid Development Kit © PLX Technology, www.plxtech.com Page 1 of 34 06Aug12, version 1.3...
- Page 2 This document contains PLX Confidential and Proprietary information. The contents of this document may not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc. PLX provides the information and data included in this document for your benefit, but it is not possible to entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products.
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Page 3: Table Of Contents
FATAL_ERR#, INTA# and GPIO LEDs ....................... 21 2.15 Reference Clock Circuitry ..........................22 2.16 Reset Circuitry ..............................22 2.17 Port Status Indicator LEDs ..........................22 2.18 Hardware Strap Pins ............................23 © PLX Technology, www.plxtech.com Page 3 of 34 06Aug12, version 1.3... - Page 4 Figure 14. Fatal Error, INTA# and GPIO LEDs ____________________________________________________________________ 21 Figure 15. Manual PERST# button ____________________________________________________________________________ 22 Figure 16: 24‐Pin ATX Power Connector _ _______________________________________________________________________ 23 Figure 17: Midbus 2.0 Probe Footprint _ ________________________________________________________________________ 24 Figure 18. x1x1 Add‐In Card Dipswitch Setting __________________________________________________________________ 25 Figure 19. x2 Add‐In Card Dipswitch Setting ____________________________________________________________________ 26 Figure 20. x1x1 Root Complex Mode Dipswitch Setting ___________________________________________________________ 27 © PLX Technology, www.plxtech.com Page 4 of 34 06Aug12, version 1.3...
- Page 5 Table 5. SW2 Functions _ ____________________________________________________________________________________ 18 Table 6. SW3 Functions _ ____________________________________________________________________________________ 18 Table 7. SW4 Functions _ ____________________________________________________________________________________ 19 Table 8. Port Indicator Blink Pattern __________________________________________________________________________ 22 Table 9. USB3382 StrapPortCfg Settings _______________________________________________________________________ 23 Table 10. Configuration Module Description ____________________________________________________________________ 29 Table 11. Power Jumper Settings _____________________________________________________________________________ 29 © PLX Technology, www.plxtech.com Page 5 of 34 06Aug12, version 1.3...
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Page 6: General Information
USB3382 (Rev-AB) Rapid Development Kit + CM108 (two x1 downstream ports, Root USB3382-AB-1D RDK Complex Mode) USB3382 (Rev-AB) Rapid Development Kit + CM110 (one x2 downstream port, Root USB3382-AB-2D RDK Complex Mode) © PLX Technology, www.plxtech.com Page 6 of 34 06Aug12, version 1.3... -
Page 7: Figure 1. Usb3382 Rdk Front View
USB3382-AIC RDK Figure 1. USB3382 RDK Front View © PLX Technology, www.plxtech.com Page 7 of 34 06Aug12, version 1.3... -
Page 8: Usb3382 Features
Poison bit End‐to‐end Cyclic Redundancy Check (ECRC) o Lane reversal o Polarity reversal o Conventional PCI‐compatible Link Power Management states L0, L0s, L1, L2/L3 Ready, and L3 (with Vaux supported) o Conventional PCI‐compatible Device Power Management states D0 and D3hot D3cold (with Vaux supported) o Active State Power Management (ASPM) o Dynamic Link speed (2.5 or 5.0 GT/s) negotiation o Dynamic Link width negotiation • Out‐of‐Band Initialization options o Serial EEPROM o I2C and SMBus (7‐bit Slave address with 100 Kbps) • Serial EEPROM interface for initializing Configuration registers and 8051 firmware • 12‐MHz oscillator with internal Phase‐Locked Loop (PLL) multiplier © PLX Technology, www.plxtech.com Page 8 of 34 06Aug12, version 1.3... -
Page 9: Usb3382 Aic Rdk Features
USB3382-AIC RDK 1.2 USB3382 AIC RDK Features • USB 3382‐AA PCI Express Gen 2 to USB 3.0 SuperSpeed Peripheral Controller • X4 Upstream goldfinger • Two downstream PCI Express x16 Slot Connectors • DIP Switches for hardware configuration of USB3382 • Socketable Serial EEPROM • Manual push‐button PERST# capability • I2C /SMBus header for Out‐of‐Band register access • JTAG header for testability © PLX Technology, www.plxtech.com Page 9 of 34 06Aug12, version 1.3... -
Page 10: Getting Started
USB3382-AIC RDK 1.3 Getting Started Figure 2. Getting Started-Addin Card Mode Follow the following steps to use the RDK in Addin card mode. 1) Plug board into PCI Express slot on motherboard. 2) Check and set dipswitches for desired port configuration. 3) Check and install the configuration module for the desired mode. 4) Check and set the power jumpers for Addin card mode operation. 5) Plug in a hard disk power connector into J2. This step is necessary; the RDK requires the 5V supply to power some of the on board components. 6) Plug in PCI Express endpoint into downstream slots if needed. 7) After all these steps are completed, system can be powered on. 8) Plug in USB device cable in the USB Standard B connector. © PLX Technology, www.plxtech.com Page 10 of 34 06Aug12, version 1.3... -
Page 11: Figure 3. Getting Started -Root Complex Mode, Self Powered
USB3382-AIC RDK Figure 3. Getting Started –Root Complex Mode, Self Powered Follow the following steps to use the RDK in Addin card mode. 1) Check and set dipswitches for desired port configuration. 2) Check and install the configuration module for the desired mode. 3) Check and set the power jumpers for Self Powered Mode operation. 4) Plug in an ATX power supply 24 pin connector power connector into J3. 5) Plug in PCI Express endpoint into downstream slots. 6) After all these steps are completed, the ATX power supply can be powered on. 7) Plug in USB device cable in the USB Standard B connector. © PLX Technology, www.plxtech.com Page 11 of 34 06Aug12, version 1.3... -
Page 12: Figure 4. Getting Started-Root Complex Mode, Bus Powered
USB3382-AIC RDK Figure 4. Getting Started-Root Complex Mode, Bus Powered Follow the following steps to use the RDK in Root Complex mode – Bus Powered. 1) Check and set dipswitches for desired port configuration. 2) Check and install the configuration module for the desired mode. 3) Check and set the power jumpers for Bus Powered Mode operation. 4) Plug in PCI Express endpoint into downstream slots. 5) Plug in USB device cable in the USB Standard B connector. © PLX Technology, www.plxtech.com Page 12 of 34 06Aug12, version 1.3... -
Page 13: Usb3382 Rdk Hardware Architecture
USB3382-AIC RDK 2 USB3382 RDK Hardware Architecture 2.1 Architecture Block Diagram Figure 5. RDK Architecture © PLX Technology, www.plxtech.com Page 13 of 34 06Aug12, version 1.3... -
Page 14: Board Components
ATX Hard Disk Connector (J2) 12 I2C Connector (JP2) 4 Power Configuration Jumpers (JP3 – 13 JP12) EEPROM Enable Jumper (JP4) 5 24 Pin ATX Power Connector (J3) 14 EEPROM Chip with Socket (U2) 6 Configuration Dipswitches (SW1‐SW4) 15 JTAG connector (JP1) 7 DSUB9 Connector (P1) 16 USB Connector (J1) 8 Configuration Module Socket (P2) 17 USB3382 Chip (Chip not installed 9 in diagram) (U1) © PLX Technology, www.plxtech.com Page 14 of 34 06Aug12, version 1.3... -
Page 15: Usb 3382 Pci Express To Usb Client Bridge
USB3382-AIC RDK Figure 6. RDK Component Locations 2.3 USB 3382 PCI Express to USB Client Bridge The USB 3382 is a PCI Express Gen 2 to USB 3.0 SuperSpeed Client Bridge. It features 2 PCI express Gen 2 x1 ports and 2 1 USB 3.0 SuperSpeed Client Port. The device comes in a 10x10mm 132 lead package. 2.4 PCI Express Upstream Port Connection The upstream x4 connector will be a x1 or x2 link connecting the USB3382 to the add‐in card male edge connector. The USB3382 RDK can plug into x1 PCI Express slots by using a PCI Express lane converter, such as PCI Express X4‐To‐X1 Converter made by Adex Electronics. © PLX Technology, www.plxtech.com Page 15 of 34 06Aug12, version 1.3... -
Page 16: Pci Express Downstream Port Connections
Standard‐B or USB 2.0 Standard‐B plug. Figure 7: USB 3.0 Standard B Port Cable and Receptacle 2.7 Clock Circuitry For the Adapter Mode configuration, the USB3382 RDK uses the PCIe RefClk provided at the male add‐in card edge connector for the USB3382 RefClk input pins. An internal clock buffer fans out this input clock to the RefClk output pins, which provide RefClk to the PCIe connectors. In the Root Complex Mode configuration, the RDK is not connected to a PCIe port on a PC. In this case, an onboard clock chip provides RefClk to the USB3382 device. This is user selectable through a dipswitch setting. The USB3382 RDK also has a 30 MHz constant frequency clock source for the USB 3.0 interface. An internal PLL will generate modulated USB 3.0 and USB 2.0 required clocks. 2.8 Hardware Strap Pin Dipswitches The USB3382 has a number of strap pins which provide the capability to perform various types of hardware initialization without the use of EEPROM. There are two main types of switches. The extended actuator dipswitches contain the main configuration dipswitches and the recessed switches control more advanced and RESERVED functions. © PLX Technology, www.plxtech.com Page 16 of 34 06Aug12, version 1.3... -
Page 17: Dipswitch Setting Tables
L = Enables SMBUS Mode SMBUS_EN# H = Enables I C Mode System Management Bus Enable Default Setting = H = If Link training sequence fails during the Configuration state, the next time the LTSSM exits the Detect state, TS UPCFG_TIMER_EN# Ordered‐Sets advertise only the 2.5 GT/s (Gen 1) data rate Link Upconfigure Timer Enable and no Autonomous Change support. If Link training © PLX Technology, www.plxtech.com Page 17 of 34 06Aug12, version 1.3... -
Page 18: Table 5. Sw2 Functions
SW3 Functional Description Switch Position Settings PROBE_MODE# Default Setting = H Factory Test Only SERDES_MODE_EN# Factory Test Only Default Setting = H PLL_BYPASS# Default Setting = H Factory Test Only FAST_BRINGUP# Factory Test Only Default Setting = H DEBUG_SEL# © PLX Technology, www.plxtech.com Page 18 of 34 06Aug12, version 1.3... -
Page 19: Serial Eeprom Interface
SW3 Functional Description Switch Position Settings DBG_PRBSEL[3:0] Default Setting = HHHH Factory Test Only GPIO3PIN Factory Test Only Default Setting = H 2.10 Serial EEPROM Interface The USB3382 RDK provides a socketed Serial EEPROM. The contents of the serial EEPROM are used to initialize the USB3382 after power‐on reset. The RDK contains a Microchip 25AA128 128K serial EEPROM device. There is a jumper JP4 that gives the option of disabling the EEPROM by disconnecting the CS# pin. Note the EEPROM device orientation as shown below. Figure 9. EEPROM in Socket © PLX Technology, www.plxtech.com Page 19 of 34 06Aug12, version 1.3... -
Page 20: Jtag Interface
2.11 JTAG Interface The USB3382 RDK contains a dedicated 2x10 JTAG header (JP2). There is no “standard” JTAG header pin arrangement; therefore, JTAG header type and pin assignments are somewhat arbitrary. The header and pin assignment chosen for this board is compatible with the Scanworks USB‐100 JTAG controller). TRST Figure 10. Pin Assignment of JTAG Port Header, JP1 2.12 I2C/SMBUS Interface The USB3382 provides a two‐wire I2C/SMBus compatible slave mode interface with three bit addressing. Through this out‐of‐band channel, the users can read, write, and configure the USB3382 internal registers, run internal output probe mode, monitor error counters, and monitor status of all ports. The USB3382 RDK provides a 10 pin I2C header (JP3). The pin header included is compatible with the Aardvark I2C/SPI Host Adapter Part Number: TP240141 by TotalPhase. Figure 11. I2C Plug Orientation © PLX Technology, www.plxtech.com Page 20 of 34 06Aug12, version 1.3... -
Page 21: 8051 Debug Port
Figure 12. Pin Assignment of I2C Connector JP2 2.13 8051 Debug port The USB3382 device has 2 signals, TXD and RXD that will interface to the 8051 internal CPU for firmware debug. These signals connect to a 9‐pin DSUB male plug connector, such as the Kycon K20XHT‐E9P‐N. Figure 13: DB9 Male Connector 2.14 FATAL_ERR#, INTA# and GPIO LEDs The USB3382 RDK device has a number of chip‐specific side band signals that are intended for various uses. The FATAL_ERR# output is used to indicate that the USB3382 device detected a fatal unrecoverable error. The INTA# output is used to be compatible with PCI. The FATAL_ERR# shall also drive a red LED indicator, and the INTA# signal shall drive an amber colored LED indicator. The General Purpose I/O pins are also brought to LEDs Figure 14. Fatal Error, INTA# and GPIO LEDs © PLX Technology, www.plxtech.com Page 21 of 34 06Aug12, version 1.3... -
Page 22: Reference Clock Circuitry
These states are shown in the table below. RDK will have a total of 2 LED indicators for Port 0 and Port 1. Table 8. Port Indicator Blink Pattern Link State LED Pattern Link Down Link Up; GEN2 Link Up; GEN1 Blinking: 0.5 sec ON, 0.5 sec OFF © PLX Technology, www.plxtech.com Page 22 of 34 06Aug12, version 1.3... -
Page 23: Hardware Strap Pins
5% of their normal values, red LED(s) will be turned on to signal the potential voltage problem to the chip. Bypass capacitors, plane capacitors, and power inductors will be use to filter out the voltage noise. © PLX Technology, www.plxtech.com Page 23 of 34... -
Page 24: Pcie Protocol Debug
The 3.3 Vaux power from the goldfinger connector is connected to the 3.3Vaux signal on the downstream slots. 1Vaux is generated from a DC/DC converter from the 5VCC supply on the ATX hard disk connector. © PLX Technology, www.plxtech.com Page 24 of 34 06Aug12, version 1.3... -
Page 25: Rdk Configurations
USB3382-AIC RDK 3 RDK Configurations The USB3382 RDK can be configured to operate in one of several modes as described in this section. The modes can be entered by changing jumpers and configuration modules. The configuration modules control the routing of the PCIE lanes and Refclk, while the jumpers set the power options of the RDK. 3.1 x1x1 Add‐In Card Strap Pin Setting Figure 18. x1x1 Add-In Card Dipswitch Setting © PLX Technology, www.plxtech.com Page 25 of 34 06Aug12, version 1.3... -
Page 26: X2 Add-In Card Strap Pin Setting
USB3382-AIC RDK 3.2 x2 Add‐In Card Strap Pin Setting Figure 19. x2 Add-In Card Dipswitch Setting © PLX Technology, www.plxtech.com Page 26 of 34 06Aug12, version 1.3... -
Page 27: X1X1 Root Complex Mode Strap Pin Setting
PORTCFG0 RC_MODE TP24 SMBUS_EN# UPCFG_TIMER_EN# TESTMODE3 TESTMODE2 TESTMODE1 TESTMODE0 CLKSEL PROBE_MODE# I2C_ADDR2 I2C_ADDR1 SERDES_MODE_EN# I2C_ADDR0 PLL_BYPASS# FAST_BRINGUP# DEBUG_SEL# LEGACY SSC_CT# DBGMODE Figure 20. x1x1 Root Complex Mode Dipswitch Setting © PLX Technology, www.plxtech.com Page 27 of 34 06Aug12, version 1.3... -
Page 28: X2 Root Complex Mode Dipswitch Setting
USB3382-AIC RDK 3.4 x2 Root Complex Mode Dipswitch Setting Figure 21. x2 Root Complex Mode Dipswitch Setting © PLX Technology, www.plxtech.com Page 28 of 34 06Aug12, version 1.3... -
Page 29: Configuration Modules
Bus Powered JP6 1‐2 1‐2 1‐2 JP7 2‐3 1‐2 1‐2 JP8 2‐3 2‐3 1‐2 JP9 1‐2 1‐2 1‐2 JP10 2‐3 2‐3 1‐2 JP11 2‐3 2‐3 1‐2 JP12 Short Short Short © PLX Technology, www.plxtech.com Page 29 of 34 06Aug12, version 1.3... -
Page 30: Figure 22: Jumper Settings For System Powered Mode
USB3382-AIC RDK Figure 22: Jumper Settings for System Powered Mode © PLX Technology, www.plxtech.com Page 30 of 34 06Aug12, version 1.3... -
Page 31: Figure 23: Jumper Settings For Self Powered Mode
USB3382-AIC RDK Figure 23: Jumper Settings for Self Powered Mode © PLX Technology, www.plxtech.com Page 31 of 34 06Aug12, version 1.3... -
Page 32: Figure 24: Jumper Settings For Bus Powered Mode
USB3382-AIC RDK Figure 24: Jumper Settings for Bus Powered Mode © PLX Technology, www.plxtech.com Page 32 of 34 06Aug12, version 1.3... -
Page 33: Appendix
USB3382-AIC RDK 4 Appendix 4.1 Board Revision Notes There are several revision of the USB 3382 RDK. This manual covers the latest Revision 002 and 003. The revision number is part of the board number etched in copper on the solder side of the board near the goldfinger. The revision is the third field of the part number. The image below shows the Rev 001 RDK. Figure 25. RDK Part Number Revision 002 and and above changes the JP9 header into a 3 pin header to tie the EN2 of the DC/DC converter to 5VCC or to GPIO0. The default setting of JP9 is on position 1‐2. Figure 26. JP9 on RDK Rev 002 © PLX Technology, www.plxtech.com Page 33 of 34 06Aug12, version 1.3... -
Page 34: Figure 27. Jp9 On Rdk Rev 001
USB3382-AIC RDK Revision 001 has a two pin jumper that that only connects GPIO0 to EN2 of the DC/DC converter, which by default should also be enabled. The default setting on RDK Rev 001 is open. Figure 27. JP9 on RDK Rev 001 © PLX Technology, www.plxtech.com Page 34 of 34 06Aug12, version 1.3...
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