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UART {0/1}
The 96Boards specifications calls for a 4-wire UART implementation, UART0 and an optimal second 2wire UART, UART1 on
the Low Speed Expansion Connector.
The WinLink E850 Development Board implements UART0 as a 4-wire UART that connects directly to the Exynos 850 SoC.
These signals are driven at 1.8V.
The WinLink E850 Development Board implements UART1 as a 2-wire UART that connects directly to the Exynos 850 SoC.
These signals are driven at 1.8V.
I2C {0/1}
The 96Boards specification calls for two I2C interfaces to be implemented on the Low Speed Expansion Connector.
The WinLink E850 Development Board implements both interfaces named I2C4 and I2C5. They connect directly to the
Exynos 850 SoC. Each of the I2C lines is pulled up to VIO18_PMU via 4.7K resistor.
GPIO {A-L}
The 96Boards specification calls for 12
GPIO lines to be implemented on the
Low Speed Expansion Connector.
All GPIO pins could be used as external
interrupt sources. GPIO A ~ L are routed
to the Exynos 850 SoC.
SPI 0
The 96Boards specification calls for one SPI bus master to be provided on the Low Speed Expansion Connector.
The WinLink E850 Development Board implements a full SPI master with 4 wires, CLK, CS, MOSI and MISO. The signals are
connected directly to the Exynos 850 SoC and driven at 1.8V.
PCM/I2S
The 96Boards specification calls for one PCM/I2S bus to be provided on the Low Speed Expansion Connector. The CLK, FS
and DO signals are required while the DI is optional.
The WinLink E850 Development Board implements a PCM/I2S interface with 4 wires, CLK, FS, DO and DI. The signals are
connected directly to the Exynos 850 SoC and driven at 1.8V.
Power and Reset
The 96Boards specification calls for a signal on the Low Speed Expansion Connector that can power on/off the board and a
signal that serves as a board reset signal.
The WinLink E850 Development Board routes the PWR_BTN_N (named POWERKEY on schematic) signal to the PWRON pin
of the PMIC S2MPU12. This signal is driven by SW4 as well, the on-board power on push-button switch. A mezzanine
implementation of this signals should not drive it with any voltage, the only allowed operation is to force it to GND to start
the board from a sleep mode.
The WinLink E850 Development Board routes the RST_BTN_N (named XNWRESET on schematic) signal to the WRSTBO pin of
the PMIC S2MPU12.
WinLink
E850-96Board
E850 96 Board GPIO Signals
GPIO-A
GPIO-C
GPIO-E
GPIO-G
GPIO-I
GPIO-K
GPIO-B
GPIO-D
GPIO-F
GPIO-H
GPIO-J
GPIO-L
Note 1) When a port is used as an output function, DISABLE the pull-up/down.
Development Board Hardware User Guide
Exynos 850 pin
Remarks
XEINT9/GPA1[1]
VDDQ18_ALIVE(1.8V) signal
XEINT10/GPA1[2]
VDDQ18_ALIVE(1.8V) signal
XEINT11/GPA1[3]
VDDQ18_ALIVE(1.8V) signal
XEINT22/GPA2[6]
VDDQ18_ALIVE(1.8V) signal
XEINT24/GPA3[0]
VDDQ18_ALIVE(1.8V) signal
XEINT26/GPA3[2]
VDDQ18_ALIVE(1.8V) signal
XEINT17/GPA2[1]
VDDQ18_ALIVE(1.8V) signal
XEINT19/GPA2[3]
VDDQ18_ALIVE(1.8V) signal
XEINT21/GPA2[5]
VDDQ18_ALIVE(1.8V) signal
XEINT23/GPA2[7]
VDDQ18_ALIVE(1.8V) signal
XEINT25/GPA3[1]
VDDQ18_ALIVE(1.8V) signal
XEINT27/GPA3[3]
VDDQ18_ALIVE(1.8V) signal
Note 2) All GPIOA~L
Pull Down with 50k internally by default
15/21
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