Nuvoton NUC442RG8AE Manuals

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Nuvoton NUC442RG8AE Technical Reference Manual

Nuvoton NUC442RG8AE Technical Reference Manual (1386 pages)

32-bit Microcontroller

Brand: Nuvoton | Category: Microcontrollers | Size: 15 MB

Table of Contents

Table of Contents
2
General Description
19
Numicro NUC442/NUC472 General Description
19
Table 1.1-1 Key Features Support Table
19
Features
20
Numicro NUC442 Features - Connectivity Series
20
Numicro NUC472 Features - Advanced Series
28
Abbreviations
36
Table 3.1-1 List of Abbreviations
37
Parts Information List and Pin Configuration
38
Selection Guide
38
Numicro NUC442 Connectivity Series Selection Guide
38
Numicro NUC472 Advanced Series Selection Guide
38
Figure 4.1-1 Numicro NUC442/NUC472 Series Selection Code
40
Pin Configuration
41
Numicro NUC442 Pin Diagrams
41
Figure 4.2-1 Numicro Nuc442Rxxxx LQFP 64-Pin Diagram
41
Figure 4.2-2 Numicro Nuc442Vxxxx LQFP 100-Pin Diagram
42
Figure 4.2-3 Numicro Nuc442Kxxxx LQFP 128-Pin Diagram
43
Figure 4.2-4 Numicro Nuc442Jxxxx LQFP 144-Pin Diagram
44
Numicro NUC472 Pin Diagrams
45
Figure 4.2-5 Numicro Nuc472Vxxxx LQFP 100-Pin Diagram
45
Figure 4.2-6 Numicro Nuc472Kxxxx LQFP 128-Pin Diagram
46
Figure 4.2-7 Numicro Nuc472Jxxxx LQFP 144-Pin Diagram
47
Figure 4.2-8 Numicro Nuc472Hxxxx LQFP 176-Pin Diagram
48
Pin Description
49
Numicro NUC442 Package LQFP 64-Pin Description
49
Numicro NUC442 Package LQFP 100-Pin Description
61
Numicro NUC442 Package LQFP 128-Pin Description
81
Numicro NUC442 Package LQFP 144-Pin Description
105
Numicro NUC472 Package LQFP 100-Pin Description
131
Numicro NUC472 Package LQFP 128-Pin Description
152
Numicro NUC472 Package LQFP 144-Pin Description
177
Numicro NUC472 Package LQFP 176-Pin Description
204
Summary GPIO Multi-Function Pin Description
234
Summary Function Pin Description
240
Block Diagram
264
Numicro NUC442 Series Block Diagram
264
Figure 5.1-1 Numicro NUC442 Series Block Diagram
264
Numicro NUC472 Series Block Diagram
265
Figure 5.2-1 Numicro NUC472 Series Block Diagram
265
Functional Description
266
ARM ® Cortex ® -M4 Core
266
Figure 6.1-1 Cortex ® -M4 Block Diagram
266
System Manager
269
Overview
269
System Reset
269
System Power Distribution
270
Figure 6.2-1 Numicro NUC442/NUC472 Power Distribution Diagram
270
System Memory Map
271
Table 6.2-1 Address Space Assignments for On-Chip Controllers
273
System Control Registers
274
System Timer (Systick)
322
Nested Vectored Interrupt Controller (NVIC)
326
Table 6.2-2 Exception Model
327
Table 6.2-3 Interrupt Number Table
331
System Control Register Map and Description
345
Table 6.2-4 Priority Grouping
349
Clock Controller
354
Overview
354
Figure 6.3-1 Clock Generator Block Diagram
355
System Clock and Systick Clock
358
Clock Monitor
358
Figure 6.3-2 System Clock Block Diagram
358
Figure 6.3-3 System Clock Switch Procedure
359
Figure 6.3-4 Systick Clock Control Block Diagram
359
Peripherals Clock
360
Power-Down Mode Clock
360
Frequency Divider Output
360
Figure 6.3-5 Clock Source of Frequency Divider
360
Figure 6.3-6 Block Diagram of Frequency Divider
361
Register Map
362
Register Description
363
Table 6.3-1 Power-Down Mode Control Table
365
Analog Comparator Controller (ACMP)
394
Overview
394
Features
394
Block Diagram
395
Figure 6.4-1 Analog Comparator Block Diagram
395
Functional Description
396
Figure 6.4-2 Comparator Controller Interrupt Sources
396
Figure 6.4-3 Comparator Hysteresis Function
396
Comparator Reference Voltage (CRV)
397
Figure 6.4-4 Comparator Reference Voltage Block Diagram
397
Register Map
398
Register Description
399
Analog-To-Digital Converter (ADC)
406
Overview
406
Features
406
Block Diagram
407
Functional Description
407
Figure 6.5-1 ADC Controller Block Diagram
407
Figure 6.5-2 ADC Clock Control
408
Figure 6.5-3 Single Mode Conversion Timing Diagram
409
Figure 6.5-4 Single-Cycle Scan on Enabled Channels Timing Diagram
410
Figure 6.5-5 Continuous Scan on Enabled Channels Timing Diagram
411
Figure 6.5-6 A/D Conversion Result Monitor Block Diagram
412
Figure 6.5-7 A/D Controller Interrupt
412
Register Map
414
Register Description
415
Figure 6.5-8 Conversion Result Mapping Diagram of Single-End Input
416
Figure 6.5-9 Conversion Result Mapping Diagram of Differential Input
417
12-Bit Analog-To-Digital Converter (Enhanced ADC)
426
Overview
426
Features
426
Block Diagram
428
Figure 6.6-1 ADC0 Converter Block Diagram
428
Operation Procedure
429
Figure 6.6-2 ADC1 Converter Block Diagram
429
Figure 6.6-3 ADC Clock Control
429
Figure 6.6-4 Single Sampling Mode Conversion Timing Diagram
431
Figure 6.6-5 SAMPLE00~SAMPLE03 and SAMPLE10~SAMPLE13 Control Block Diagram
431
Figure 6.6-6 SAMPLE04~SAMPLE07 and SAMPLE14~SAMPLE17 Control Block Diagram
432
Figure 6.6-7 SAMPLE Module Conversion Priority Arbitrator Diagram
433
Figure 6.6-8 PWM-Triggered ADC Start Conversion
434
Figure 6.6-9 SAMPLE Module A/D EOC Signal for ADINT0 Interrupt
435
Figure 6.6-10 SAMPLE Module A/D EOC Signal for ADINT1 Interrupt
436
Figure 6.6-11 SAMPLE Module A/D EOC Signal for ADINT2 Interrupt
436
Figure 6.6-12 SAMPLE Module A/D EOC Signal for ADINT3 Interrupt
437
Figure 6.6-13 Conversion Start Delay Timing Diagram
438
Figure 6.6-14 A/D Extend Sampling Timing Diagram
439
Figure 6.6-15 A/D Conversion Result Monitor Logics Diagram
439
Figure 6.6-16 A/D Controller Interrupts
440
Register Map
441
Register Description
444
Controller Area Network (CAN)
475
Overview
475
Features
475
Block Diagram
476
Figure 6.7-1 CAN Peripheral Block Diagram
476
Functional Description
477
Test Mode
478
Figure 6.7-2 CAN Core in Silent Mode
478
Figure 6.7-3 CAN Core in Loop Back Mode
479
Figure 6.7-4 CAN Core in Loop Back Mode Combined with Silent Mode
479
CAN Communications
480
Figure 6.7-5 Data Transfer between if N Registers and Message
482
Table 6.7-1 Initialization of a Transmit Object
484
Table 6.7-2 Initialization of a Receive Object
485
Figure 6.7-6 Application Software Handling of a FIFO Buffer
487
Figure 6.7-7 Bit Timing
489
Figure 6.7-8 Propagation Time Segment
490
Table 6.7-3 CAN Bit Time Parameters
490
Figure 6.7-9 Synchronization on "Late" and "Early" Edges
492
Figure 6.7-10 Filtering of Short Dominant Spikes
493
Figure 6.7-11 Structure of the CAN Core's CAN Protocol Controller
495
Register Description
499
Register Map
499
CAN Interface Reset State
500
Table 6.7-4 CAN Register Map for each Bit Function
503
Table 6.7-5 Error Code
507
Table 6.7-6 Source of Interrupts
510
Table 6.7-7 IF1 and IF2 Message Interface Register
513
Table 6.7-8 Structure of a Message Object in the Message Memory
527
CRC Controller
538
Overview
538
Features
538
Block Diagram
539
Basic Configuration
539
Figure 6.8-1 CRC Generator Block Diagram
539
Functional Description
540
Register Map
540
Register Description
541
Cryptographic Accelerator
546
Overview
546
Features
546
Block Diagram
547
Figure 6.9-1 Cryptographic Accelerator Block Diagram
547
Functional Description
548
Figure 6.9-2 PRNG Function Diagram
549
Figure 6.9-3 Electronic Codebook Mode
550
Figure 6.9-4 Cipher Block Chaining Mode
551
Figure 6.9-5 Cipher Feedback Mode
552
Figure 6.9-6 Output Feedback Mode
553
Figure 6.9-7 Counter Mode
554
Figure 6.9-8 CBC-CS1 Encryption
555
Figure 6.9-9 CBC-CS1 Decryption
555
Table 6.9-1 Comparison of SHA Functions
557
Register Map
559
Register Description
564
PDMA Controller (PDMA)
609
Overview
609
Features
609
Block Diagram
609
Functional Description
609
Figure 6.10-1 PDMA Controller Block Diagram
609
Table 6.10-1 Memory Map of Embedded Descriptor Table
610
Figure 6.10-2 Embedded Description Table Data Structure
611
Figure 6.10-3 Embedded Description Table Data Structure
612
Figure 6.10-4 Embedded Description Table Data Structure
613
Table 6.10-2 Channel Priority Table
613
Register Map
615
Register Description
620
External Bus Interface (EBI)
657
Overview
657
Features
657
Block Diagram
658
Functional Description
658
Figure 6.11-1 EBI Block Diagram
658
Figure 6.11-2 Connection of 16-Bit EBI Data Width with 16-Bit Device
659
Figure 6.11-3 Connection of 8-Bit EBI Data Width with 8-Bit Device
660
Figure 6.11-4 Connection of 16-Bit EBI Data Width with 16-Bit Device in Address/Data Separating Mode
660
Table 6.11-1 Timing Control Parameter Settings
661
Figure 6.11-5 Timing Control Waveform for 16-Bit Data Width
662
Figure 6.11-6 Timing Control Waveform for 8-Bit Data Width
663
Figure 6.11-7 Timing Control Waveform for Insert Idle Cycle
664
Figure 6.11-8 Timing Control Waveform for Address & Data Separate Mode (16-Bit Data Width)
665
Register Map
666
Register Description
667
Ethernet MAC Controller (EMAC) (NUC472 Only)
680
Overview
680
Features
680
Block Diagram
681
Figure 6.12-1 Ethernet MAC Controller Block Diagram
681
Functional Description
682
Table 6.12-1 Arbiter Arbitration Results
682
Figure 6.12-2 Ethernet Frame Format
683
Figure 6.12-3 64-Bit Reference Timing Counter
684
DMA Descriptors Data Structure
685
Figure 6.12-4 RXDMA Descriptor Data Structure
685
Figure 6.12-5 TXDMA Descriptor Data Structure
691
Register and Memory Map
698
Register Description
701
Table 6.12-2 Different CAMCMR Setting and Type of Received Packet
703
Figure 6.12-6 MII Management Frame Format
718
Table 6.12-3 MII Management Function Configure Sequence
718
Flash Memory Controller (FMC)
753
Overview
753
Features
753
Block Diagram
754
Flash Memory Organization
754
Table 6.13-1 Memory Address Map
754
Figure 6.13-1 Flash Memory Organization
755
Boot Selection
756
Table 6.13-2 NUC442/NUC472 Boot Selection
756
In Application Programming
757
Figure 6.13-2 NUC442/NUC472 Boot Selection
757
Data Flash
758
Figure 6.13-3 Executable Range of Code with IAP Function Enabled
758
Figure 6.13-4 Flash Memory Structure
759
User Configuration
760
In System Program (ISP)
765
ISP Procedure
765
Table 6.13-3 ISP Mode Command
768
Flash Control Register Map
769
Flash Control Register Description
770
General Purpose I/O (GPIO)
789
Overview
789
Features
789
Functional Description
790
Figure 6.14-1 Push-Pull Output
790
Figure 6.14-2 Open-Drain Output
790
Figure 6.14-3 Quasi-Bidirectional I/O Mode
791
Register Map
792
Register Description
801
I 2 C Serial Interface Controller (Master/Slave)
820
Overview
821
Figure 6.15-1 I 2 C Bus Timing
821
Features
822
Functional Description
823
Figure 6.15-2 I 2 C Protocol
823
Figure 6.15-3 Master Transmits Data to Slave
823
Figure 6.15-4 Master Reads Data from Slave
824
Figure 6.15-5 START and STOP Condition
824
Operation Modes
825
Figure 6.15-6 Bit Transfer on I 2 C Bus
825
Figure 6.15-7 Acknowledge on I 2 C Bus
825
Figure 6.15-8 Control I
826
Figure 6.15-9 Master Transmitter Mode Control Flow
827
Figure 6.15-10 Master Receiver Mode Control Flow
828
Figure 6.15-11 Slave Mode Control Flow
829
Figure 6.15-12 GC Mode
831
Figure 6.15-13 EEPROM Random Read
832
Protocol Registers
833
Figure 6.15-14 Protocol of EEPROM Random Read
833
Figure 6.15-15 I 2 C Data Shifting Direction
834
Figure 6.15-16 I 2 C Time-Out Count Block Diagram
836
Table 6.15-1 I 2 C Status Code Description Table
836
Register Map
838
Register Description
839
I 2 S Controller (I 2 S)
849
Overview
849
Features
849
Block Diagram
850
Figure 6.16-1 I 2 S Clock Control Diagram
850
Figure 6.16-2 I 2 S Controller Block Diagram
850
Timing Diagram Description
851
Figure 6.16-3 I 2 S Bus Timing Diagram (PCM = 0, Format = 0)
851
Figure 6.16-4 MSB Justified Timing Diagram (PCM = 0, Format = 1)
851
Figure 6.16-5 PCM a Audio Timing Diagram (PCM = 1, Format = 0)
851
Figure 6.16-6 PCM B Audio Timing Diagram (PCM = 1, Format = 1)
852
Figure 6.16-7 FIFO Contents for Various I
853
Functional Description
854
Figure 6.16-8 Master Mode Interface Block Diagram
854
Figure 6.16-9 Slave Mode Interface Block Diagram
854
Register Map
855
Register Description
856
Image Capture Interface (ICAP)
868
Overview
868
Block Diagram
868
Features
868
Figure 6.17-1 Image Capture Interface Block Diagram
868
Functional Description
869
Figure 6.17-2 Image Capture Flow Chart
869
Figure 6.17-3 Image Start and Size of the Window after Cropping Block
870
Figure 6.17-4 MDSM Is Set to 0 and MDBS Is Set to 1
870
Figure 6.17-5 MDSM Is Set to 1 and MDBS Is Set to 0
871
Register Map
872
Register Description
873
Enhanced Input Capture Timer
903
Overview
903
Features
903
Input Capture Timer/Counter Architecture
903
Figure 6.18-1 Input Capture Timer/Counter Clock Source Control
903
Input Noise Filter
904
Operation of Input Capture Timer/Counter
904
Figure 6.18-2 Input Capture Timer/Counter Architecture
904
Figure 6.18-3 Noise Filter Sampling Clock Selection
904
Figure 6.18-4 Input Capture Timer/Counter Functions Block
906
Input Capture Timer/Counter Interrupt Architecture
907
Figure 6.18-5 Input Capture Timer/Counter Interrupt Architecture Diagram
907
Register Map
908
Register Description
909
OP Amplifier
919
Overview
919
Features
919
Block Diagram
920
Interrupt Sources
920
Figure 6.19-1 OP Amplifier Block Diagram
920
Register Map
921
Register Description
922
PS/2 Device Controller (PS2D)
925
Overview
925
Features
925
Block Diagram
926
Figure 6.20-1 PS/2 Device Block Diagram
926
Functional Description
927
Figure 6.20-2 Data Format of Device-To-Host
928
Figure 6.20-3 Data Format of Host-To-Device
928
Figure 6.20-4 PS/2 Bit Data Format
929
Figure 6.20-5 PS/2 Bus Timing
929
Figure 6.20-6 PS/2 Data Format
930
Register Map
931
Register Description
932
PWM Generator and Capture Timer (PWM)
939
Overview
939
Features
939
Block Diagram
940
Figure 6.21-1 PWM Generator 0 Clock Source Control
940
Figure 6.21-2 PWM Generator 0 Architecture Diagram
941
Figure 6.21-3 PWM Generator 2 Clock Source Control
942
Figure 6.21-4 PWM Generator 2 Architecture Diagram
943
Figure 6.21-5 PWM Generator 4 Clock Source Control
944
Functional Description
945
Figure 6.21-6 PWM Generator 4 Architecture Diagram
945
Figure 6.21-7 PWM Waveform of Edge-Aligned Type
946
Figure 6.21-8 Center-Aligned Mode Output Waveform
947
Figure 6.21-9 PWM Center Aligned Interrupt Generate Timing Waveform
948
Figure 6.21-10 PWM Double Buffering Timing Waveform
949
Figure 6.21-11 PWM Paired-Output with Dead-Zone Generation Operation
949
Figure 6.21-12 Illustration of Mask Control Waveform
951
Figure 6.21-13 PWM Brake Function
952
Figure 6.21-14 PWM Output Multiplex for Group Mode and Synchronous Mode
953
Figure 6.21-15 PWM Multiplex for Mask Control, Brake Control and Polarity Control
954
Figure 6.21-16 Capture Operation Timing
955
Figure 6.21-17 PWM Interrupt Architecture Diagram
956
Register Map
958
Register Description
961
Enhanced PWM Generator (EPWM)
998
Overview
998
Features
998
PWM Operation
999
Figure 6.22-1 PWM Block Diagram
999
Figure 6.22-2 PWM Clock Source Control
999
Figure 6.22-3 PWM Time-Base Generator
1000
Figure 6.22-4 Edge-Aligned PWM
1002
Figure 6.22-5 PWM0 Edge Aligned Waveform Output
1002
Figure 6.22-6 Edge-Aligned Flow Diagram
1003
Figure 6.22-7 Center-Aligned Mode
1004
Figure 6.22-8 Example PWM0 Center-Aligned Waveform Output
1005
PWM Brake
1006
Figure 6.22-9 Center-Aligned Flow Diagram (INTTYPE (EPWM_CTL[8]) = 0)
1006
Figure 6.22-10 PWM Brake Function
1007
Figure 6.22-11 PWM Brake Condition (Edge-Aligned Mode)
1008
Figure 6.22-12 PWM Brake Condition (Centre-Aligned Mode)
1008
PWM Port Output Driving Control
1009
PWM Modes
1009
Figure 6.22-13 PWM Output Driving Control
1009
Figure 6.22-14 Dead-Time Insertion
1010
Polarity Control
1011
Figure 6.22-15 Initial State and Polarity Control with Rising Edge Dead Time Insertion
1011
PWM Mask Output Function
1012
Figure 6.22-16 Illustration of Mask Control
1013
Asymmetric PWM Output
1014
Figure 6.22-17 Asymmetric PWM Architecture
1015
Figure 6.22-18 Symmetric PWM Output in Centre Aligned Mode
1015
Figure 6.22-19 Asymmetric PWM Output for Asprldm=00B
1015
Interrupt Architecture of Enhanced PWM
1016
Figure 6.22-20 Asymmetric PWM Output for Asprldm=01B
1016
Figure 6.22-21 Asymmetric PWM Output for Asprldm=10B
1016
Figure 6.22-22 Enhanced PWM Interrupt Architecture
1017
Register Map
1018
Register Description
1019
Quadrature Encoder Interface (QEI)
1039
Overview
1039
Features
1039
QEI Architecture
1039
Figure 6.23-1 QEI Clock Source Control
1039
Input Noise Filter
1040
Figure 6.23-2 QEI Block Diagram
1040
Operation of Quadrature Encoder Interface
1041
Figure 6.23-3 Noise Filter
1041
Figure 6.23-4 Noise Filter Sampling Clock Selection
1041
Figure 6.23-5 QEA/QEB/IDX Timing Requirement through Noise Filter
1041
Figure 6.23-6 X4 Counting Mode
1042
Figure 6.23-7 X2 Counting Mode
1043
Table 6.23-1 Direction of Count
1044
Compare Function
1045
Reload Counter by Pin IDX
1045
Figure 6.23-8 Compare Operation
1045
Figure 6.23-9 QEI_CNT Reload/Reset Control
1045
Capture QEI Counter
1046
Figure 6.23-10 Trigger Control of Capturing QEI Counter
1046
QEI Interrupt Architecture
1047
Figure 6.23-11 Capture and Latch QEI Counter
1047
Figure 6.23-12 Quadrature Encoder Interface Interrupt Architecture Diagram
1048
Register Map
1049
Register Description
1050
Real Time Clock (RTC)
1060
Overview
1060
Features
1060
Block Diagram
1061
Figure 6.24-1 RTC Block Diagram
1061
Figure 6.24-2 Tamper Detector and Spare Register
1061
Functional Description
1062
Register Map
1065
Register Description
1067
Smart Card Host Interface (SC)
1090
Overview
1090
Features
1090
Block Diagram
1090
Functional Description
1091
Figure 6.25-1 SC Clock Control Diagram (4-Bit Prescale Counter in Clock Controller)
1091
Figure 6.25-2 SC Controller Block Diagram
1091
Figure 6.25-3 SC Data Character
1092
Figure 6.25-4 SC Activation Sequence
1092
Figure 6.25-5 SC Warm Reset Sequence
1093
Figure 6.25-6 SC Deactivation Sequence
1094
Figure 6.25-7 Initial Character TS
1095
Figure 6.25-8 SC Error Signal
1095
Register Map
1099
Register Description
1100
Secure Digital Host Controller
1126
Overview
1126
Features
1126
Block Diagram and Card Pad Assignment
1127
SD Host DMA Controller
1127
Figure 6.26-1 SD Host Controller Block Diagram
1127
Table 6.26-1 SD/SDHC Pad Assignment
1127
SD Host Functional Description
1128
Register Map
1130
Register Description
1131
Serial Peripheral Interface (SPI)
1151
Overview
1151
Features
1151
Block Diagram
1152
Figure 6.27-1 SPI Block Diagram
1152
Functional Description
1153
Figure 6.27-2 SPI Master Mode Application Block Diagram
1153
Figure 6.27-3 SPI Slave Mode Application Block Diagram
1154
Figure 6.27-4 32-Bit in One Transaction
1155
Figure 6.27-5 Byte Reorder Function
1156
Figure 6.27-6 Timing Waveform for Byte Suspend
1156
Figure 6.27-7 2-Bit Mode System Architecture
1157
Figure 6.27-8 2-Bit Mode (Slave Mode)
1158
Figure 6.27-9 Bit Sequence of Dual Output Mode
1159
Figure 6.27-10 Bit Sequence of Dual Input Mode
1159
Figure 6.27-11 Bit Sequence of Quad Output Mode
1160
Figure 6.27-12 Bit Sequence of Quad Input Mode
1160
Figure 6.27-13 FIFO Mode Block Diagram
1161
Timing Diagram
1164
Figure 6.27-14 SPI Timing in Master Mode
1164
Figure 6.27-15 SPI Timing in Master Mode (Alternate Phase of SPICLK)
1165
Figure 6.27-16 SPI Timing in Slave Mode
1165
Programming Flows
1166
Figure 6.27-17 SPI Timing in Slave Mode (Alternate Phase of SPICLK)
1166
Register Map
1169
Register Description
1170
Timer Controller (TIMER)
1184
Overview
1184
Features
1184
Block Diagram
1185
Figure 6.28-1 Timer Controller Block Diagram
1185
Figure 6.28-2 Clock Source of Timer Controller
1185
Basic Configuration
1186
Functional Description
1186
Figure 6.28-3 Continuous Counting Mode
1188
Register Map
1189
Register Description
1191
Watchdog Timer (WDT)
1201
Overview
1201
Features
1201
Block Diagram
1201
Figure 6.29-1 Watchdog Timer Clock Control
1201
Basic Configuration
1202
Functional Description
1202
Figure 6.29-2 Watchdog Timer Block Diagram
1202
Table 6.29-1 Watchdog Timer Interval Selection
1203
Figure 6.29-3 Timing of Interrupt and Reset Signal
1204
Register Map
1205
Register Description
1206
Window Watchdog Timer (WWDT)
1209
Overview
1209
Features
1209
Block Diagram
1209
Figure 6.30-1 Window Watchdog Timer Clock Control
1209
Figure 6.30-2 Window Watchdog Timer Block Diagram
1209
Basic Configuration
1210
Functional Description
1210
Table 6.30-1 Window Watchdog Prescaler Value Selection
1210
Figure 6.30-3 Window Watchdog Timer Reset and Reload Behavior
1211
Table 6.30-2 CMPDAT Setting Limitation
1211
Register Map
1212
Register Description
1213
UART Interface Controller (UART)
1218
Overview
1218
Features
1218
Block Diagram
1220
Figure 6.31-1 UART Clock Control Diagram
1220
Figure 6.31-2 UART Block Diagram
1221
Irda Mode
1222
Figure 6.31-3 Auto Flow Control Block Diagram
1222
Figure 6.31-4 Irda Block Diagram
1223
LIN (Local Interconnection Network) Mode
1224
Figure 6.31-5 Irda TX/RX Timing Diagram
1224
Figure 6.31-6 LIN Frame Structure
1225
Figure 6.31-7 Break Detection in LIN Mode
1227
Figure 6.31-8 Relationship between Break Detection and Frame Error Detection
1228
Figure 6.31-9 LIN Sync Field Measurement
1231
Figure 6.31-10 UART_BAUD Update Method
1232
Function Mode
1233
Figure 6.31-11 RS-485 Frame Structure
1235
Register Map
1236
Register Description
1237
Table 6.31-1 UART Interrupt Sources and Flag List in DMA Mode
1252
Table 6.31-2 UART Interrupt Sources and Flag List in Software Mode
1252
Table 6.31-3 Baud Rate Equation Table
1255
Table 6.31-4 Baud Rate Equation Table
1255
USB 2.0 Device Controller
1266
Overview
1266
Features
1266
Block Diagram
1267
Functional Description
1267
Figure 6.32-1 USB Device Controller Block Diagram
1267
Registers Map
1270
Register Description
1275
USB 1.1 Host Controller (USBH)
1327
Overview
1327
Features
1327
Block Diagram
1328
Basic Configuration
1328
Figure 6.33-1 USB 1.1 Host Controller Block Diagram
1328
Functional Description
1329
Register Map
1331
Register Description
1333
USB OTG Controller
1365
Overview
1365
Features
1365
Block Diagram
1366
Functional Description
1366
Figure 6.34-1 USB OTG Controller Block Diagram
1366
Figure 6.34-2 HOST-Only Mode
1367
Figure 6.34-3 Device-Only Mode
1367
Figure 6.34-4 ID-Dependent (ID Low)
1368
Figure 6.34-5 ID-Dependent (ID High)
1368
Figure 6.34-6 OTG Device
1369
Register and Memory Map
1370
Register Description
1371
Package Dimensions
1380
LQFP 64L (10X10X1.4 MM Footprint 2.0 MM)
1380
LQFP 100L (14X14X1.4 MM Footprint 2.0 MM)
1381
LQFP 128L (14X14X1.4 MM Footprint 2.0 MM)
1382
LQFP 144L (20X20X1.4 MM Footprint 2.0 MM)
1383
LQFP 176L (24X24X1.4 MM Footprint 2.0 MM)
1384
Revision History
1385

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