Motherboard Block Diagram - Supermicro SuperServer 621H-TN12R User Manual

Motherboard Block Diagram

JPCIe2A1
MCIO
JSLOT1
Gen Z 4C CONN
JPCIe2B1
MCIO
BMC
NCSI
NCSI
DDR4
PCIe
DDR4
MEMORY
LPC/eSPI
SPI2
USB
SPI2
BMC
UART
BMC
BMC FLASH/
64MB VGA
TPM/FW SPI
Flash/TPM
PHY
EMMC
EMMC
SPI1
P1H P1G P1F P1E
PE2 PE1 PE0
#1 #1 #1 #1
DMI
CPU 1
#2 #2 #2 #2
CH4
Socket E
CH4
SocketID 00
VCCP1
CH5
CH6
PE3 PE4
CPU #1
VR14
P1_NVMe1
MCIO
FOR NVMe x8 PORT
PCIe Gen5 x16 (128GB/s)
P1_NVMe0
MCIO
FOR NVMe x8 PORT
X13DEM
AIOM1
Gen 4C+ CONN AIOM1 OCP SIDEBAND
PCH
NCSI
USB 2.0
JUSB3
USB 3.1
USB3.1[8,9]
USB3.0 x 2
JS1
SlimSAS
SATA 6Gb/s
NCSI CONN
SATA Gen3 [0..7]
NCSI
FOR SATA
HDR
x8 PORT
PCIE[11]
PICe Gen1
eSPI eSPI
USB2.0 USB2.0 [0,1]
J48
UART
IO CONN
COM
1920x1200 32bpps 60Hz VGA
USB(4,6)
USB2.0[4,6]
PHY
MDI LAN
RTL8211F
DMI x8
UID
DMI Gen3 x8 (8GB/s)
UPI 16GT/s (Min), 24GT/s (Tar)
UPI 16GT/s (Min), 24T/s (Tar)
Shadowed Core
P1A P1B P1C P1D
UP0 UPI1
#1 #1 #1 #1
#2 #2 #2 #2
CH0
CH1
CH2
CH3
UPI2
UPI3
UPI 16GT/s (Min), 24GT/s (Tar)
UPI 16GT/s (Min), 24GT/s (Tar)
P1_NVMe3
MCIO
FOR NVMe x8 PORT
PCIe Gen5 x16 (128GB/s)
P1_NVMe2
MCIO
FOR NVMe x8 PORT
Figure 1-8. Motherboard Block Diagram
20
M2_A CONN
JPCIe3A1
JSLOT4
Gen Z 4C CONN
MCIO
JPCIe3B1
MCIO
JPF2
USB 2.0 [2,7]
PCIe/S-SATA Gen3
PCIe G3 x2/SATA G3 x1
PCIe/S-SATA Gen3
SPI
BIOS SPI
USB 2.0 JAIOM2SB1
OCP SIDEBAND
SPI1
P2H P2G P2F P2E
UPI0 UPI1
#1 #1 #1 #1
CPU 2
#2 #2 #2 #2
CH4
Socket E
CH5
SocketID 01
VCCP2
CH6
CH7
UPI3 UPI2
P2_NVMe2
MCIO
FOR NVMe x8 PORT
PCIe Gen5 x16 (128GB/s)
P2_NVMe3
MCIO
P2_NVMe1
FOR NVMe x8 PORT
MCIO
FOR NVMe x8 PORT
PCIe Gen5 x16 (128GB/s)
P2_NVMe0
MCIO
FOR NVMe x8 PORT
Chapter 1: Introduction
M2_B CONN
JPCIe5A1 JPCIe5B1
MCIO
MCIO
CPLD
BIOS
64MB Flash
BIOs SPI
CPLD
Con Memory
4Mbit
AIOM2 OCP SIDEBAND
SPI2
UID BUTTON
BMC SPI1
AIOM1 OCP SIDEBAND
AIOM1 OCP SIDEBAND
P2A P2B P2C P2D
PE2 PE1 PE0
#1 #1 #1 #1
#2 #2 #2 #2
CH0
CH1
CH2
CH3
PE4 PE3
CPU #2
VR14
MUX
SPI2
BMC