Transformer protection RET650
Version 1.1 ANSI
Scheme communication
Logic
Table 42. Tripping logic SMPPTRC (94)
Function
Trip action
Timers
Table 43. Configurable logic blocks
Logic block
Quantity with cycle time
5 ms
AND
60
OR
60
XOR
10
INVERTER
30
SRMEMORY
10
RSMEMORY
10
GATE
10
PULSETIMER
10
TIMERSET
10
LOOPDELAY
10
46
Range or value
3-ph
(0.000-60.000) s
Range or value
20 ms
100 ms
60
160
-
60
160
-
10
20
-
30
80
-
10
20
-
10
20
-
10
20
-
10
20
(0.000–90000.000) s
10
20
(0.000–90000.000) s
10
20
© Copyright 2011 ABB Power Grids. All rights reserved
M12380-1 v4
Accuracy
-
± 0.5% ± 10 ms
M11443-1 v6
1MRK 504 127-BUS B
IP11406-1 v1
Accuracy
-
-
-
-
-
-
-
± 0.5% ± 25 ms
± 0.5% ± 25 ms
ABB Power Grids