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CoreLink™ GIC-600AE Generic Interrupt Controller Issue: 04 Technical Reference Manual Feedback Arm welcomes feedback on this product and its documentation. To provide feedback on the product, create a ticket on https:/ /support.developer.arm.com. To provide feedback on the document, fill the following survey: https:/ /developer.arm.com/...
® Glossary is a list of terms used in Arm documentation, together with definitions for those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning. See the Arm Glossary for more information: developer.arm.com/glossary.
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The SM is a confidential document that is only available to licensees. Development Interface Report The DIR describes the activities conducted by Arm that are related to the safety architecture of the GIC-600AE. The DIR is a confidential document that is only available to licensees.
PPIs and return wires must be the same for all cores sharing a Redistributor. Level-sensitive PPI signals are active-LOW by default, as with previous Arm GIC implementations. However, individual PPI signals can be inverted and synchronized using the following build-time parameters: •...
MSI-64. See 3.4 MSI-64 Encapsulator on page If the ITS is placed downstream of an ACE interconnect, care must be taken to avoid system deadlock. For more information, see Functional integration in the Arm ® CoreLink ™...
The SPI Collator wires can be extended to create other functions. By default, the asserted level of an SPI is active-HIGH, as with previous Arm GIC implementations. However, each SPI can be either inverted, synchronized, or both, using the parameters...
ITS blocks in the system. The configuration produces a balanced tree structure with minimum Clock Domain Crossings (CDCs). The Arm internal scripts limit a single interconnect crossbar to 16 destinations. To work around this limitation, you can use domains in the config file. For example, instead of 32 Redistributors in one domain, you can use two domains that each contain 16.
The GIC-600AE uses affinity routing, a hierarchical scheme, to identify connected cores and for routing interrupts to specific cores. The Arm architecture defines a register in a core that identifies the logical address of the core in the system. This register, which is known as the Multiprocessor Identification Register (MPIDR), has a hierarchical format.
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By default, all 1 of N SPIs can go to both classes, so the interrupt class feature is disabled by default. The system can use this partitioning for any purpose, for example in an Arm big.LITTLE system, all the ®...
In small configurations, these caches might be too small to be worth the overhead of implementing them as SRAM. If ECC protection is not required for a cache that is implemented as an array of flops, and to reduce RAM area, you can remove ECC from each RAM individually. See the Arm ®...
6.10 P-Channel and Q-Channel protection on page 232 for more information. 6.4.3 AMBA interface FuSa ports The following interfaces add the parity extended chk signal bits, as specified in the Arm AMBA ® Parity Extensions. In the following table, Granularity refers to the hierarchy or the block in which the ports are relevant.
The following parameters apply to PPI and SPI interrupt interface protection. • fusa_spi_prot • fusa_ppi_prot For more information about these parameters, see Configuration options in the Arm ® CoreLink ™ GIC-600AE Generic Interrupt Controller Configuration and Integration Manual. 6.12 Systematic fault watchdog protection The GIC-600AE contains a watchdog-based PING/ACK mechanism that guards against systematic errors on the interconnect.
Scan enable 6.13.3 LBIST Arm has verified that a third-party LBIST controller can be instanced and used to control the scan chains and obtain additional latent fault coverage or diagnostic information. 6.14 Generic fault inputs Each GIC block has generic fault inputs that allow the SoC integrator to connect and flag external faults through the FMU.
Mechanisms. For more information, see 6.10.4 Disabling P-Channel and Q-Channel Safety Mechanisms page 238. For more information about these parameters, see the Configuration options chapter of the Arm ® CoreLink ™ GIC-600AE Generic Interrupt Controller Configuration and Integration Manual.
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