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ARM CoreLink GIC-600AE Technical Reference Manual

Generic interrupt controller
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Arm
CoreLink™ GIC-600AE Generic Interrupt
®
Controller
Revision: r0p3
Technical Reference Manual
Non-Confidential
Copyright © 2018–2020, 2022 Arm Limited (or its
affiliates).
All rights reserved.
Issue 04
101206_0003_04_en

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Summary of Contents for ARM CoreLink GIC-600AE

  • Page 1 CoreLink™ GIC-600AE Generic Interrupt ® Controller Revision: r0p3 Technical Reference Manual Non-Confidential Issue 04 101206_0003_04_en Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
  • Page 2 No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.
  • Page 3 Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company.
  • Page 4 CoreLink™ GIC-600AE Generic Interrupt Controller Issue: 04 Technical Reference Manual Feedback Arm welcomes feedback on this product and its documentation. To provide feedback on the product, create a ticket on https:/ /support.developer.arm.com. To provide feedback on the document, fill the following survey: https:/ /developer.arm.com/...

  • Page 5: Table Of Contents

    3.3 Interrupt Translation Service........................34 3.3.1 ITS ACE-Lite subordinate interface...................... 36 3.3.2 ITS ACE-Lite manager interface......................37 3.3.3 ITS AXI4-Stream interface........................38 3.3.4 ITS Q-Channel............................39 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 5 of 268...
  • Page 6 4.6.2 Processor core power management..................... 57 4.6.3 Other power management........................58 4.7 Getting started.............................. 60 4.8 Backwards compatibility..........................60 4.9 ITS..................................60 4.9.1 ITS cache control, locking, and test......................61 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 6 of 268...
  • Page 7 5.2.5 GICD_SAC, Secure Access Control register..................106 5.2.6 GICD_CHIPSR, Chip Status Register....................107 5.2.7 GICD_DCHIPR, Default Chip Register....................109 5.2.8 GICD_CHIPR<n>, Chip Registers....................... 109 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 7 of 268...
  • Page 8 5.6.6 GITS_CFGID, Configuration ID Register................... 145 5.6.7 GITS_PIDR2, Peripheral ID2 Register....................146 5.7 ITS translation register summary......................147 5.8 GICT register summary..........................148 5.8.1 GICT_ERR<n>FR, Error Record Feature Register................149 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 8 of 268...
  • Page 9 5.10.7 FMU_PINGNOW, Ping Now register....................186 5.10.8 FMU_SMEN, Safety Mechanism Enable register................. 187 5.10.9 FMU_SMINJERR, Safety Mechanism Inject Error register............189 5.10.10 FMU_PINGMASK, Ping Mask register..................190 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 9 of 268...
  • Page 10 6.7.3 RAM scrubbing............................221 6.8 External interface protection........................221 6.8.1 ACE-Lite interface parity protection....................222 6.8.2 AXI4-Stream interface parity protection................... 224 6.8.3 APB interface parity protection......................225 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 10 of 268...
  • Page 11 A.6 Miscellaneous signals..........................258 A.7 Interblock AXI4-Stream interface signals..................... 260 A.8 Interdomain signals............................262 A.9 Interchip AXI4-Stream interface signals....................262 B. Implementation-defined features......................263 C. Revisions..............................265 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 11 of 268...

  • Page 12: Introduction

    ® Glossary is a list of terms used in Arm documentation, together with definitions for those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning. See the Arm Glossary for more information: developer.arm.com/glossary.
  • Page 13 Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 14: Useful Resources

    101209 Confidential ® CoreLink ™ GIC-600AE Generic Interrupt Controller Development Interface Report 101208 Confidential ® CoreLink ™ GIC-600AE Generic Interrupt Controller Safety Manual Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 14 of 268...
  • Page 15 Standard Manufacturer’s Identification Code JEP106 JEDEC Arm tests its PDFs only in Adobe Acrobat and Acrobat Reader. Arm cannot guarantee the quality of its documents when used with any other PDF reader. Adobe PDF reader products can be downloaded at http:/ /www.adobe.com...

  • Page 16: About The Gic-600Ae

    Interrupt Translation Service (ITS) block. The Distributor also maintains the coherency of the SPI register space in multichip configurations. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 16 of 268...
  • Page 17 GIC from a single combined block or a set of individual blocks that are interconnected using your own transport layer. These blocks can be combined in different ways: Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 17 of 268...
  • Page 18 The following figure shows a GIC-600AE with interconnect in an example system. The cross-chip interfaces enable communication between cores in a multichip configuration. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 18 of 268...
  • Page 19 Programming Memory interface controller Key: Cross-chip interfaces components Free-flowing channel The following figure shows a monolithic GIC-600AE with interconnect in an example system. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 19 of 268...

  • Page 20: Compliance

    Controller Architecture Specification, GIC architecture version 3 and version • The AMBA ACE-Lite protocol. See the AMBA AXI and ACE Protocol Specification. ® ® Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 20 of 268...

  • Page 21: Features

    • The following interrupt groups allow interrupts to target different Exception levels: ◦ Group 0 ◦ Non-secure Group 1 ◦ Secure Group 1 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 21 of 268...

  • Page 22: Test Features

    flow can mean that some behaviors that the TRM describes are not relevant. If you are programming the GIC-600AE, contact: Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 22 of 268...

  • Page 23: Product Revisions

    The SM is a confidential document that is only available to licensees. Development Interface Report The DIR describes the activities conducted by Arm that are related to the safety architecture of the GIC-600AE. The DIR is a confidential document that is only available to licensees.
  • Page 24 • Bug fixes • The GICA registers are renamed to GICM registers. See 5.3 Distributor registers (GICM) for message-based SPIs summary on page 117. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 24 of 268...

  • Page 25: Components And Configuration

    The Distributor is the main communication point between all GIC-600AE blocks. It performs SPI management and LPI caching, and all communications with other blocks and chips. The following figure shows the Distributor and its interfaces. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 25 of 268...

  • Page 26: Distributor Axi4-Stream Interfaces

    Distributor and a single Redistributor block. Packets must never be interleaved. For information about AXI4-Stream signals, see the AMBA ® 4 AXI4-Stream Protocol Specification. The following table lists the AXI4-Stream input interfaces. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 26 of 268...

  • Page 27: Distributor Ace-Lite Subordinate Interface

    The a<x>user_s[2:0] signals are not used and must be tied LOW. The following table shows the acceptance capabilities of the Distributor ACE-Lite subordinate interface. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 27 of 268...

  • Page 28: Distributor Ace-Lite Manager Interface

    256-bit aligned read and writes to any Pending table 3 8-bit read and writes to any Pending table 256-bit aligned reads to the Property table Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 28 of 268...

  • Page 29: Distributor Q-Channels

    As the qactive output signal includes combinatorial and asynchronous inputs, then you must consider qactive as an asynchronous output. For more information, see the AMBA ® Low Power Interface Specification. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 29 of 268...

  • Page 30: Distributor P-Channel

    For more information, see the Arm ® CoreLink ™ GIC-600AE Generic Interrupt Controller Configuration and Integration Manual. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 30 of 268...

  • Page 31: Redistributor

    Configuration and Integration Manual for more information. The Redistributor (GICR) registers are programmed through the Distributor ACE-Lite subordinate port. The Distributor also contains the architectural LPI functionality. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 31 of 268...

  • Page 32: Redistributor Axi4-Stream Interface

    Q-Channel denies a quiescence request that it receives on the qreqn signal, by asserting the qdeny signal. For more information, see the AMBA Low Power Interface ® Specification. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 32 of 268...

  • Page 33: Redistributor Ppi Signals

    PPIs and return wires must be the same for all cores sharing a Redistributor. Level-sensitive PPI signals are active-LOW by default, as with previous Arm GIC implementations. However, individual PPI signals can be inverted and synchronized using the following build-time parameters: •...

  • Page 34: Interrupt Translation Service

    In accordance with PCIe dependency rules, read responses on a PCIe Root Complex subordinate port must be ordered against completion of posted writes on a Root Complex manager port. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 35 60. The following figure provides an example of the ITS integration process. Figure 3-4: ITS integration PCIe root complex SMMU Interconnect Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 35 of 268...

  • Page 36: Its Ace-Lite Subordinate Interface

    MSI-64. See 3.4 MSI-64 Encapsulator on page If the ITS is placed downstream of an ACE interconnect, care must be taken to avoid system deadlock. For more information, see Functional integration in the Arm ® CoreLink ™...

  • Page 37: Its Ace-Lite Manager Interface

    The ACE-Lite manager port issues accesses to the ITS private tables and Command queue. If the bypass switch is configured, the port also forwards transactions from the subordinate interface. The Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 38: Its Axi4-Stream Interface

    We expect that a typical distributed system is 16 bits wide. When a pre-existing wide interconnect is used, the 64-bit option allows messages to be efficiently packed. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 39: Its Q-Channel

    Figure 3-8: GIC-600AE top-level structure options on page 47. For more information, see the Arm CoreLink GIC-600AE Generic Interrupt Controller Configuration ® ™ and Integration Manual. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 39 of 268...

  • Page 40: Encapsulator

    MSI-64 ACE-Lite manager interface This interface is a full ACE-Lite manager port. The following table shows the transaction acceptance capabilities of both subordinate and manager ports. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 40 of 268...

  • Page 41: Encapsulator Configuration

    Specifies the width of rid signal 1-32 RID_WIDTH FWD_REG_TYPE Register slice type on forward AW, AR, and W channels None Reverse Forward Full Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 41 of 268...

  • Page 42: Spi Collator

    The SPI Collator wires can be extended to create other functions. By default, the asserted level of an SPI is active-HIGH, as with previous Arm GIC implementations. However, each SPI can be either inverted, synchronized, or both, using the parameters...

  • Page 43: Spi Collator Power Q-Channel

    In low-power mode, it is only safe to stop the SPI Collator clock if all edge-triggered interrupts into the SPI Collator are pulse extended so that edges are not missed. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 44: Spi Collator Configuration

    The power controller must ignore the wake_request signal until the core is powered down. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 44 of 268...

  • Page 45: Wake Request Axi4-Stream Interface

    Apart from the cross-chip communications, GIC-600AE provides an AXI4-Stream interconnect for transporting messages. However, messages can be sent over an existing interconnect provided the interconnect is free-flowing. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 45 of 268...

  • Page 46: Interconnect Configuration

    ITS blocks in the system. The configuration produces a balanced tree structure with minimum Clock Domain Crossings (CDCs). The Arm internal scripts limit a single interconnect crossbar to 16 destinations. To work around this limitation, you can use domains in the config file. For example, instead of 32 Redistributors in one domain, you can use two domains that each contain 16.
  • Page 47 ACE-Lite subordinate interface Distributor Cross-chip interfaces ACE-Lite manager interface Interconnect Interconnect Redistributor Interconnect Redistributor Redistributor Redistributor GIC Stream interfaces GIC Stream interfaces GIC Stream interface Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 47 of 268...

  • Page 48: Operation

    The GIC-600AE provides an option, through parameters, to include one or both a synchronizer and inverter on each PPI interrupt signal. See 3.2.4 Redistributor PPI signals on page 33 for more information. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 48 of 268...

  • Page 49: Spis

    LPIs. The ITS provides INTID translation, allowing peripherals to be owned directly by a virtual machine if an SMMU is also present for those peripherals. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 49 of 268...

  • Page 50: Choosing Between Lpis And Spis

    LPIs that occur more frequently. Therefore, we recommend using SPIs for any latency-sensitive interrupts that are expected to occur infrequently. For more information, see the GICv3 and GICv4 Software Overview. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 50 of 268...

  • Page 51: Interrupt Groups And Security

    Group 1 Secure Non-secure Secure EL0, EL1 Non-secure EL0, EL1, EL2 configuration parameter controls the GIC-600AE security, as the GIC exits reset. ds_value Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 51 of 268...

  • Page 52: Physical Interrupt Signals (Ppis And Spis)

    4.3 Physical interrupt signals (PPIs and SPIs) The GIC-600AE supports two types of physical interrupt signal. The two types of physical interrupt signal are: Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 52 of 268...

  • Page 53: Affinity Routing And Assignment

    The GIC-600AE uses affinity routing, a hierarchical scheme, to identify connected cores and for routing interrupts to specific cores. The Arm architecture defines a register in a core that identifies the logical address of the core in the system. This register, which is known as the Multiprocessor Identification Register (MPIDR), has a hierarchical format.

  • Page 54: Spi Routing And 1 Of N Selection

    When the relevant GICD_IROUTERn.Interrupt_Routing_Mode == 1, the GIC selects an appropriate core for an SPI. When GICD_IROUTERn.Interrupt_Routing_Mode == 0, the SPI is routed to the core specified by the remaining fields of GICD_IROUTERn. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 54 of 268...
  • Page 55 By default, all 1 of N SPIs can go to both classes, so the interrupt class feature is disabled by default. The system can use this partitioning for any purpose, for example in an Arm big.LITTLE system, all the ®...

  • Page 56: Power Management

    This requirement is true for all GIC-600AE configurations. GICR_PWRR register can control Redistributor power management either by operating through the core, or through the Redistributor. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 56 of 268...

  • Page 57: Processor Core Power Management

    1. Mask interrupts on the core. 2. Clear the CPU interface enables. 3. Set the interrupt bypass disable on the CPU interface. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 57 of 268...

  • Page 58: Other Power Management

    LPIs. The implementation-defined powerdown sequence must: 1. Complete the powerdown sequence for all cores. 2. Set GICR_WAKER.Sleep to 1. 3. Poll GICR_WAKER until GICR_WAKER.Quiescent is set. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 58 of 268...
  • Page 59 GICR_CTLR.Enable_LPIs bit is set, or when the GICR_WAKER.Sleep and GICR_WAKER.Quiescent bits are both set. For more information, see the GICv3 and GICv4 Software Overview. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 59 of 268...

  • Page 60: Getting Started

    Device table Collection table CollectionID DeviceID base Target, address Interrupt Translation collection EventID Table (ITT) base, size DeviceID size pINTID, collection ITT base, size Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 60 of 268...

  • Page 61: Its Cache Control, Locking, And Test

    In small configurations, these caches might be too small to be worth the overhead of implementing them as SRAM. If ECC protection is not required for a cache that is implemented as an array of flops, and to reduce RAM area, you can remove ECC from each RAM individually. See the Arm ®...

  • Page 62: Its Commands And Errors

    ACE-Lite subordinate interface write translation errors. Only when the ITS has a separate ACE-Lite GITS_FCTLR.AEE (Access Error subordinate port. Enable) Translation errors on incoming writes to GITS_TRANSLATER GITS_FCTLR.UEE (Unmapped Error Enable) Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 62 of 268...

  • Page 63: Lpi Caching

    LPIs that have the same INTID. However the system is designed to reorder and sort the cache over time. In some circumstances, this behavior can cause duplicated interrupts to not be Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 64: Memory Access And Attributes

    The mappings are designed for the Armv8 and Armv8.2 generation of cores. However, setting this bit converts the GIC-600AE to full featured mapping. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 64 of 268...

  • Page 65: Msi-64

    To prevent rogue software accessing the GITS_TRANSLATER register and spoofing any device, we recommend that the GITS_TRANSLATER register is moved to an arbitrary page that is protected by the hypervisor. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 65 of 268...

  • Page 66: Rams And Ecc

    If single or double errors are detected, they are reported in the software visible error records, see 4.15 Reliability, Accessibility, and Serviceability on page 68 for more information. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 66 of 268...

  • Page 67: Performance Monitoring Unit

    6. Enable the global count enable in GICP_CR.E PMU registers, other than enables, do not have resets and must be programmed before use. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 67 of 268...

  • Page 68: Reliability, Accessibility, And Serviceability

    Double Error Detection (SECDED), and Scrub, software and bus error reporting. The GIC makes all necessary information available to software through Armv8.2 RAS architecture- compliant register space. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 68 of 268...

  • Page 69: Non-Secure Access

    When an ECC error is detected, the GIC-600AE attempts to contain the error and ensure it cannot propagate further. The following table shows the GIC behavior when errors are detected in each RAM. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 69 of 268...

  • Page 70: Error Recovery And Fault Handling Interrupts

    ID field that must be programmed to 0 if internal routing is not required, or if internal routing is required, to a legally supported SPI ID. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 71: Error Handling Records

    GICT_ERR<n>STATUS.SERR == 14, illegal access. One record per ITS on the chip. Records 13+ are not present if an ITS is not present. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 71 of 268...
  • Page 72 GICR_WAKER.Sleep handshake already in use. is complete. 4.6.3 Other power management on page Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 72 of 268...
  • Page 73 SGI RAM or PPI RAM. Check records 4 space that has encountered an and 8, and perform a recovery sequence for those uncorrectable error. interrupts. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 73 of 268...
  • Page 74 Software must not attempt to clear nonexistent An attempt was made to clear an Data, bits[15:0] LPIs OOR interrupt. Only valid when GICR LPI injection registers are supported. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 74 of 268...
  • Page 75 LPI ID, bits[15:0] table, where an error response was interrupt to be lost around the specified LPI. received with the data. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 75 of 268...
  • Page 76 2 = Uncorrectable ID, bits[log (SPIs) − 1:0] The RAM address can be determined from the ID >> 1. ID[0] specifies the SPI RAM number. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 76 of 268...
  • Page 77 SGI RAM error record 3 records RAM ECC errors that are correctable. SGI RAM error record 4 records RAM ECC errors that are uncorrectable. SGI RAM error records 3-4 are present if SGI RAM ECC is configured. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 77 of 268...
  • Page 78 GICR_IGRPMODR0, and GICR_NSACR bits to their default values. The values of PPIs are not changed. 7. Reprogram the interrupt to the intended settings. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 78 of 268...
  • Page 79 LPI RAM error records 9-10 are present if LPI support is configured. The LPI RAM is the main LPI cache and it stores the LPI properties and pending information. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 80 Bit location, bits[x + 9:x + 2] • • RAM, bits[x + 1:x] • ITS, bits[x − 1:0] Where x = log (ITS) Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 80 of 268...
  • Page 81 MAPD_ITTSIZE_OOR 0x10802 0 A command has tried to allocate an ITT table that is larger than the supported EventID size Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 81 of 268...
  • Page 82 A MAPVI has tried to map an interrupt to a device that is not mapped MAPVI_ID_OOR 0x10A05 0 A MAPVI has tried to use an EventID that is outside the size that the corresponding MAPD command supports Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 82 of 268...
  • Page 83 DISCARD_ID_OOR 0x10F05 0 A DISCARD command has tried to use an EventID that is outside the size that the corresponding MAPD command supports Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 83 of 268...
  • Page 84 0x10C26 1 An INV has tried to invalidate an interrupt with a physical ID that is larger than the target supports. See GICR_PROPBASER.IDbits. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 84 of 268...
  • Page 85 ITS supports. See GITS_BASER0, and for information about the supported range, see GITS_TYPER. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 85 of 268...
  • Page 86 INVALID_COMMAND 0x10F00 1 An invalid command has been detected in the Command queue. Software must correct this and then resume. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 86 of 268...

  • Page 87: Bus Errors

    Read-only SYN_GICR_CORRUPTED Data read from SGI or PPI RAM is corrupted Read-only SYN_ITS_OFF Access to ITS attempted when powered down Read and write Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 87 of 268...

  • Page 88: Multichip Operation

    • The Routing table can only process one operation at a time. Therefore, software must ensure that GICD_DCHIPR.PUP == 0 before commencing any operation such as writes to GICD_CHIPRx or GICD_DCHIPR. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 88 of 268...

  • Page 89: Connecting The Chips

    You can designate a different chip later if necessary. 4. In a single register write, program GICD_CHIPRx with: a) GICD_CHIPRx.ADDR so that each chip can forward messages to chip x. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 89 of 268...

  • Page 90: Changing The Routing Table Owner

    1. Write to GICD_DCHIPR.rt_owner with a value that selects the appropriate chip to be the Routing table owner. The chip_id signal sets the identification value of a chip. 2. Poll for GICD_DCHIPR.PUP == 0. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 90 of 268...

  • Page 91: Spi Ownership For Multichip Operation

    If you have saved register values and intend to restore them, you must use the OFF state and restore the Routing table first, before attempting to restore any SPI registers. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 92: Isolating A Chip From The System

    Q-Channel must have also accepted before the reset can occur. This might require masking interrupts outside of the GIC to ensure that all interrupt lines have reached their idle state. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 92 of 268...

  • Page 93: Spi Operation For Multichip Operation

    16 × (the number of configured SPI blocks). SPI 1 of N The GIC-600AE never sends a 1 of N SPI to another chip. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 93 of 268...

  • Page 94: Lpi Multichip Operation

    If software attempts to access a chip that does not exist, is offline, or access a core that does not exist, the request is dropped and reported through the ITS command and translation error records. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 95: Programmers Model

    The following table shows the register map pages. Table 5-1: Register map pages Page offset Page Description GICD 5.2 Distributor registers (GICD/GICDA) summary on page 98 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 95 of 268...
  • Page 96 GICD page is at 32-bit address 0xFFFF0000, the tie-off is 16-bit 0xFFFF. See A.6 Miscellaneous signals on page 258 for information about the gicd_page_offset and its_transr_page_offset tie-off signals. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 96 of 268...

  • Page 97: Discovery

    Therefore, the chip_id signal value must be set before the GIC exits from reset. For more information, see the GICv3 and GICv4 Software Overview. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 97 of 268...

  • Page 98: Gic-600Ae Register Access And Banking

    GICD_IIDR Distributor Implementer Identification Register 0x0008 0x030nn43B The nn value depends on the rxpy identifier. Reserved 0x000C- 0x001C GICD_FCTLR Function Control Register 0x0020 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 98 of 268...
  • Page 99 The existence of this register depends on the configuration of the GIC-600AE. If Security support is not included, then this register does not exist. This register is only accessible from a Secure access. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 99 of 268...
  • Page 100 Component ID 0 Register 0xFFF4 GICD_CIDR1 0xF0 Component ID 1 Register 0xFFF8 GICD_CIDR2 Component ID 2 Register 0x05 0xFFFC GICD_CIDR3 Component ID 3 Register 0xB1 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 100 of 268...

  • Page 101: Gicd_Ctlr, Distributor Control Register

    Reset [31] Register Write Pending: No register write in progress Register write in progress [30:8] Reserved E1NWF Enable 1 of N Wakeup Functionality Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 101 of 268...

  • Page 102: Gicd_Typer, Interrupt Controller Type Register

    27 26 25 24 23 19 18 17 16 15 11 10 9 8 7 Reserved IDbits num_LPIs ITLinesNumber Number MBIS Reserved No1N LPIS SecurityExtn DVIS Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 102 of 268...

  • Page 103: Gicd_Iidr, Distributor Implementer Identification Register

    This register provides information about the implementer and revision of the Distributor. Configurations This register is available in all configurations. Attributes Width 32-bit Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 103 of 268...

  • Page 104: Gicd_Fctlr, Function Control Register

    Distributor. The register is not distributed and only acts on the local chip. Configurations This register is available in all configurations. Attributes Width 32-bit Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 104 of 268...
  • Page 105 [17:16] NSACR Non-secure access control. Values are as described in the GICD_NSACR register. This is the value that is used if an SPI has an error. Secure access only. Resets to 0b00. [15:14] - Reserved, returns 0b00 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 105 of 268...

  • Page 106: Gicd_Sac, Secure Access Control Register

    5.2 Distributor registers (GICD/GICDA) summary on page 98 for the address offset, type, and reset value of this register. Usage constraints Only accessible by Secure accesses. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 106 of 268...

  • Page 107: Gicd_Chipsr, Chip Status Register

    32-bit Functional group See 5.2 Distributor registers (GICD/GICDA) summary on page 98 for the address offset, type, and reset value of this register. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 107 of 268...
  • Page 108 0b01 updating 0b10 consistent 0b11 Reserved Reserved, RES0 Gating transaction ongoing: no accesses accesses ongoing Gating status: not gated gated Reserved, RES0 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 108 of 268...

  • Page 109: Gicd_Dchipr, Default Chip Register

    Each register controls the configuration of the chip in a multichip system. This register exists on each chip in a multichip configuration and is identified by the chip number. Configurations This register is available in all multichip configurations. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 109 of 268...
  • Page 110 This bit returns the power update status: Power update complete Power update in progress SocketState This bit controls the state of the chip: Chip is offline Chip is online Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 110 of 268...

  • Page 111: Gicd_Iclarn, Interrupt Class Registers

    The SPI that a bit refers to, depends on its bit position and the base address offset of the GICD_ICLARn, that is, SPI = 16×n + bit[number]/2. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 112: Gicd_Icerrrn, Interrupt Clear Error Registers

    This register contains information that enables test software to determine if the GIC-600AE system is compatible. Configurations This register is available in all configurations. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 112 of 268...
  • Page 113 LPI supported [11:8] Reserved, returns zero [7:4] CNUM Chip number [3:1] Reserved, returns zero Socket online status: chip is offline chip is online Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 113 of 268...

  • Page 114: Gicd_Pidr4, Peripheral Id4 Register

    This register returns byte[3] of the peripheral ID. The GICD_PIDR3 register is part of the set of Distributor peripheral identification registers. Configurations This register is available in all configurations. Attributes Width 32-bit Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 114 of 268...

  • Page 115: Gicd_Pidr2, Peripheral Id2 Register

    5.2 Distributor registers (GICD/GICDA) summary on page 98 for the address offset, type, and reset value of this register. Usage constraints There are no usage constraints. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 115 of 268...

  • Page 116: Gicd_Pidr1, Peripheral Id1 Register

    Usage constraints There are no usage constraints. Bit descriptions Figure 5-15: GICD_PIDR1 bit assignments Reserved DES_0 PART_1 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 116 of 268...

  • Page 117: Gicd_Pidr0, Peripheral Id0 Register

    PART_0 Returns 0x92, which represents bits[7:0] of the 12-bit part number of the Distributor. Together, PART_0 and GICD_PIDR1.PART_1 field values indicate the part number of the Distributor. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 118: Distributor Registers (Gicm) For Message-Based Spis Summary

    The existence of this register depends on the configuration of the GIC-600AE. If Security support is not included, this register does not exist. This register is only accessible from a Secure access. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 118 of 268...

  • Page 119: Gicm_Typer, Message-Based Type Register

    Returns 1 to indicate that the register reports information about the capabilities of the frame [30] Returns 1 to indicate that the GICM_CLRSPI registers are present Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 119 of 268...

  • Page 120: Gicm_Iidr, Message-Based Distributor Implementer Identification Register

    Indicates the product ID: 0x03 GIC-600AE [23:20] - Reserved, RAZ [19:16] Variant Indicates the major revision, or variant, of the product rmpn identifier: Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 120 of 268...

  • Page 121: Redistributor Registers For Control And Physical Lpis Summary

    This register is only accessible from a Secure access. Parts of this register are architecture defined and the other parts are microarchitecture defined. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 121 of 268...
  • Page 122 The existence of this register depends on the configuration of the GIC-600AE. If ITS and LPI support is not included, this register does not exist. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 122 of 268...

  • Page 123: Gicr_Iidr, Redistributor Implementation Identification Register

    Indicates the major revision, or variant, of the product rmpn identifier: [15:12] Revision Indicates the minor revision of the product rmpn identifier: [11:0] Implementer Identifies the implementer: 0x43B Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 123 of 268...

  • Page 124: Gicr_Typer, Redistributor Type Register

    Reserved, returns 0b000000 [25:24] CommonLPIAff Returns: 0b00 Single chip configuration 0b01 If chip set by AF3 0b10 If chip set by AF2 0b11 Reserved Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 124 of 268...

  • Page 125: Gicr_Waker, Power Management Control Register

    5.4 Redistributor registers for control and physical LPIs summary on page 121 for the address offset, type, and reset value of this register. Usage constraints There are no usage constraints. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 125 of 268...

  • Page 126: Gicr_Fctlr, Function Control Register

    5.4 Redistributor registers for control and physical LPIs summary on page 121 for the address offset, type, and reset value of this register. Usage constraints There are no usage constraints. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 126 of 268...

  • Page 127: Gicr_Pwrr, Power Register

    5.4 Redistributor registers for control and physical LPIs summary on page 121 for the address offset, type, and reset value of this register. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 127 of 268...
  • Page 128 If all other cores in the Redistributor group have RDPD == 1, then setting this bit to 1 also sets RDGPD = 1. Related information Redistributor power management on page 56 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 128 of 268...

  • Page 129: Gicr_Classr, Class Register

    5.4 Redistributor registers for control and physical LPIs summary on page 121 for the address offset, type, and reset value of this register. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 129 of 268...

  • Page 130: Redistributor Registers For Sgis And Ppis Summary

    Interrupt Set-Enable Register 0x0100 Reserved 0x0104- 0x017C GICR_ICENABLER0 Interrupt Clear-Enable Register 0x0180 0x0184- Reserved 0x01FC 0x0200 GICR_ISPENDR0 PPI wire dependent Interrupt Set-Pending Register Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 130 of 268...
  • Page 131 GICR_SGIDR SGI Default Register Reserved 0xC018- 0xEFFC GICR_CFGID0 Configuration dependent 32 Configuration ID0 Register 0xF000 0xF004 GICR_CFGID1 Configuration dependent 32 Configuration ID1 Register Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 131 of 268...

  • Page 132: Gicr_Miscstatusr, Miscellaneous Status Register

    Returns the status of the wake_request signal: wake_request signal is not active wake_request signal is asserted [29:5] - Reserved AccessType Returns the access type: Secure access Non-secure access Reserved Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 132 of 268...

  • Page 133: Gicr_Ierrvr, Interrupt Error Valid Register

    This register enables you to debug this scenario. For more information, see the ® Generic Interrupt Controller Architecture Specification, GIC architecture version 3 and version Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 133 of 268...

  • Page 134: Gicr_Sgidr, Sgi Default Register

    1 = Allow Non-secure access to interrupt <n> [60, 56, 52, 48, 44, 40, 36, 32, 28, 24, 20, 16, 12, 8, 4, 0] Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 134 of 268...

  • Page 135: Gicr_Cfgid0, Configuration Id0 Register

    The ppi_id[15:0] tie-off signal sets the value of the ID. Each Redistributor must have a unique Related information Miscellaneous signals on page 258 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 135 of 268...

  • Page 136: Gicr_Cfgid1, Configuration Id1 Register

    The number of cores that this Redistributor supports. GIC-600AE supports up to 64 cores, so the maximum value of this field is 0x3F. [3:0] Reserved, RAZ Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 136 of 268...

  • Page 137: Its Control Register Summary

    GITS_CFGID Configuration dependent Configuration ID Register Reserved 0xF004- 0xFFCC GITS_PIDR4 Peripheral ID 4 Register 0xFFD0 0x44 GITS_PIDR5 Peripheral ID 5 Register 0xFFD4 0x00 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 137 of 268...

  • Page 138: Gits_Iidr, Its Implementer Identification Register

    Variant Revision Implementer Table 5-37: GITS_IIDR bit descriptions Bits Name Function [31:24] ProductID Indicates the product ID: 0x03 GIC-600AE [23:20] - Reserved, RAZ Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 138 of 268...

  • Page 139: Gits_Typer, Its Type Register

    Reserved CIDBits 24 23 20 19 18 17 13 12 4 3 2 1 0 Reserved DevBits IDBits SEIS ITTEntrySize Physical Reserved Virtual Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 139 of 268...

  • Page 140: Gits_Fctlr, Function Control Register

    RAMs. The register is not distributed and only acts on the local chip. Configurations This register is available in all configurations that have one or more ITS blocks. Attributes Width 32-bit Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 140 of 268...
  • Page 141 DMA Enable translation memory reads through the Distributor to meet PCIe dependency requirements: All memory accesses through ACE-Lite manager interface Enable translation memory reads through Distributor Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 141 of 268...
  • Page 142 Writes ignored if the ITS is not quiescent. Latency tracking enable: Disable latency tracking of interrupts Enable latency tracking of interrupts Writes ignored if the ITS is not quiescent. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 142 of 268...

  • Page 143: Gits_Opr, Operations Register

    There are no usage constraints. Bit descriptions Figure 5-32: GITS_OPR bit assignments 60 59 52 51 LOCK_ Reserved DEVICE_ID TYPE 16 15 Reserved EVENT_ID Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 143 of 268...

  • Page 144: Gits_Opsr, Operation Status Register

    5.6 ITS control register summary on page 136 for the address offset, type, and reset value of this register. Usage constraints There are no usage constraints. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 144 of 268...

  • Page 145: Gits_Cfgid, Configuration Id Register

    5.6 ITS control register summary on page 136 for the address offset, type, and reset value of this register. Usage constraints There are no usage constraints. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 145 of 268...

  • Page 146: Gits_Pidr2, Peripheral Id2 Register

    5.6 ITS control register summary on page 136 for the address offset, type, and reset value of this register. Usage constraints There are no usage constraints. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 146 of 268...

  • Page 147: Its Translation Register Summary

    0x0040 GITS_TRANSLATER WO - ITS Translation Register. See the Generic Interrupt Controller ® Architecture Specification, GIC architecture version 3 and version Reserved 0x0044- 0xFFFC Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 147 of 268...

  • Page 148: Gict Register Summary

    Component ID 0 register GICT_CIDR1 Component ID 1 register 0xFFF4 0xF0 GICT_CIDR2 Component ID 2 register 0xFFF8 0x05 0xFFFC GICT_CIDR3 0xB1 Component ID 3 register Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 148 of 268...

  • Page 149: Gict_ErrFr, Error Record Feature Register

    Fault handling interrupt for uncorrected errors. Depending on the configuration, returns either: 0b00 The GIC-600AE does not provide a fault handling interrupt 0b10 The GIC-600AE provides a controllable fault handling interrupt Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 149 of 268...

  • Page 150: Gict_ErrCtlr, Error Record Control Register

    Table 5-47: GICT_ERR<n>CTLR bit descriptions Bits Name Description [63:16] - Reserved, RAZ [15] 0 = An error response to a transaction is reported [14:9] Reserved, RAZ Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 150 of 268...

  • Page 151: Gict_ErrStatus, Error Record Primary Status Register

    Figure 5-38: GICT_ERR<n>STATUS bit assignments 31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 Reserved IERR SERR Reserved Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 151 of 268...

  • Page 152: Gict_ErrAddr, Error Record Address Register

    This register contains the address and security status of the write. This register is only present for GICT software record 0. Configurations This register is available in all configurations. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 152 of 268...

  • Page 153: Gict_ErrMisc0, Error Record Miscellaneous Register 0

    This register contains the corrected error counter and information that assists with identifying the RAM in which the error was detected. Configurations This register is available in all configurations. Attributes Width 64-bit Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 153 of 268...
  • Page 154 4.15.6.7 ITS command and translation error records 13 and beyond on page 81 The following table shows the Data field encoding for each error record and syndrome. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 154 of 268...
  • Page 155 Software error 0x13, SYN_GICD_CORRUPTED GICT_ERR0ADDR is populated Data was read from GICD register space that encountered an uncorrectable error. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 155 of 268...
  • Page 156 An attempt was made to invalidate an interrupt when Data, bits[15:0] LPIs are not enabled. Only valid when GICR LPI injection registers are supported. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 156 of 268...
  • Page 157 SGI RAM errors (4) Reserved (5) Reserved (6) Correctable Table 4-11: PPI RAM errors, 0x00 PPI RAM records 7-8 on page 79 errors (7) Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 157 of 268...

  • Page 158: Gict_ErrMisc1, Error Record Miscellaneous Register 1

    If GICD_SAC.GICTNS == 0, then only Secure software can access the functions of this register. If GICT_ERR10STATUS.MV == 1, then GICT_ERR10MISC1 ignores writes. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 158 of 268...

  • Page 159: Gict_Errgsr, Error Group Status Register

    5.8 GICT register summary on page 147 for the address offset, type, and reset value of this register. Usage constraints There are no usage constraints. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 159 of 268...

  • Page 160: Gict_Errirqcr, Error Interrupt Configuration Registers

    Bit descriptions Figure 5-43: GICT_ERRIRQCR<n> bit assignments 10 9 Reserved SPIID Table 5-54: GICT_ERRIRQCR<n> bit descriptions Bits Name Description [31:10] - Reserved, RAZ Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 160 of 268...

  • Page 161: Gict_Devid, Device Configuration Register

    Usage constraints If GICD_SAC.GICTNS == 0, then only Secure software can read this register. Bit descriptions Figure 5-44: GICT_DEVID bit assignments 16 15 Reserved Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 161 of 268...

  • Page 162: Gict_Pidr2, Peripheral Id2 Register

    Indicates that a JEDEC-assigned JEP106 identity code is used [2:0] DES_1 Bits[6:4] of the JEP106 identity code. Bits[3:0] of the JEP106 identity code are assigned to GICT_PIDR1[7:4]. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 162 of 268...

  • Page 163: Gicp Register Summary

    0xFE8 0x3B GICP_PIDR3 Peripheral ID 3 Register 0xFEC 0x00 0xFF0 GICP_CIDR0 0x0D Component ID 0 Register 0xFF4 GICP_CIDR1 0xF0 Component ID 1 Register Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 163 of 268...

  • Page 164: Gicp_Evcntrn, Event Counter Registers

    These registers configure which events that event counter n counts. The GIC-600AE supports five counters, n = 0-4. Configurations This register is available in all configurations. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 164 of 268...
  • Page 165 Set to core SPIs and LPIs Target/ID range DN_SET1OFN Set to core, which is a 1 of N interrupt Target/ID range Reserved UP_MSG Upstream message from core Target Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 165 of 268...
  • Page 166 LPI command coming in from cross-chip Target/ID 0x2C range/Chip LPI_OWN_STORED LPI stored in own location. Prevents clock gating and Q-Channel clock gating. 0x30 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 166 of 268...
  • Page 167 Interrupt taken out of Pending table (also covered PT_MATCH) Target/ID range 0x68 PT_BLOCK_SENT_CC Pending table block that is sent as part of MOVALL None 0x70 SPI_CC_LATENCY SPIs outstanding Chip Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 167 of 268...

  • Page 168: Gicp_Svrn, Shadow Value Registers

    Table 5-61: GICP_SVRn bit descriptions Bits Name Description [31:0] COUNT Captured counter value. This field holds the captured counter values of the corresponding entry in GICP_EVCNTRn. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 168 of 268...

  • Page 169: Gicp_Frn, Filter Registers

    0b11110111_11110111 matches with values of 0b11110111_1111xxxx for FilterType content 0b11110111_11110110 matches with values of 0b11110111_1111011x for FilterType content • • 0b11110101_11111111 matches with values of 0b111101xx_xxxxxxxx for FilterType content Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 169 of 268...

  • Page 170: Gicp_Cntenset0, Counter Enable Set Register 0

    This register contains the counter disables for each event counter. The GIC-600AE supports five event counters. Configurations This register is available in all configurations. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 170 of 268...

  • Page 171: Gicp_Intenset0, Interrupt Contribution Enable Set Register 0

    5.9 GICP register summary on page 163 for the address offset, type, and reset value of this register. Usage constraints There are no usage constraints. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 171 of 268...

  • Page 172: Gicp_Intenclr0, Interrupt Contribution Enable Clear Register 0

    163 for the address offset, type, and reset value of this register. Usage constraints There are no usage constraints. Bit descriptions Figure 5-53: GICP_INTENCLR0 bit assignments Reserved INTEN Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 172 of 268...

  • Page 173: Gicp_Ovsclr0, Overflow Status Clear Register 0

    There are no usage constraints. Bit descriptions Figure 5-54: GICP_OVSCLR0 bit assignments Reserved Table 5-67: GICP_OVSCLR0 bit descriptions Bits Name Description [31:5] - Reserved, RAZ Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 173 of 268...

  • Page 174: Gicp_Ovsset0, Overflow Status Set Register 0

    There are no usage constraints. Bit descriptions Figure 5-55: GICP_OVSSET0 bit assignments Reserved Table 5-68: GICP_OVSSET0 bit descriptions Bits Name Description [31:5] - Reserved, RAZ Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 174 of 268...

  • Page 175: Gicp_Capr, Counter Shadow Value Capture Register

    CAPTURE A write of 1 triggers a capture of all values within the PMU into their respective shadow registers. A write of 0 has no effect. Snapshot on page 68 for information about other snapshot event triggers. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 175 of 268...

  • Page 176: Gicp_Cfgr, Configuration Information Register

    5.9.13 GICP_CR, Control Register This register controls whether all counters are enabled or disabled. Configurations This register is available in all configurations. Attributes Width 32-bit Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 176 of 268...

  • Page 177: Gicp_Irqcr, Interrupt Configuration Register

    5.9 GICP register summary on page 163 for the address offset, type, and reset value of this register. Usage constraints There are no usage constraints. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 177 of 268...

  • Page 178: Gicp_Pidr2, Peripheral Id2 Register

    5.9 GICP register summary on page 163 for the address offset, type, and reset value of this register. Usage constraints There are no usage constraints. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 178 of 268...

  • Page 179: Fmu Register Summary

    WO 0x0 Safety Mechanism Inject Error register FMU_PINGMASK Ping Mask register 0xEC0 FMU_STATUS FMU Status register 0xF00 0xFC8 FMU_ERRIDR 0x2C Error Record ID Register Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 179 of 268...

  • Page 180: Fmu_ErrFr, Error Record Feature Register

    Error recovery interrupt is supported and controllable using FMU_ERR<n>CTLR.UI [3:2] Reserved, RAZ [1:0] Error reporting and logging. Returns: 0b10 Error reporting and logging is controllable using FMU_ERR<n>CTLR.ED Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 180 of 268...

  • Page 181: Fmu_ErrCtlr, Error Record Control Register

    Error reporting and logging is disabled for this record Error reporting and logging is enabled for this record. This setting occurs at reset. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 181 of 268...

  • Page 182: Fmu_ErrStatus, Error Record Primary Status Register

    • Do not write to an FMU_ERR<n>STATUS that corresponds to a powered-off block. See Power management on page 208. Bit descriptions Figure 5-63: FMU_ERR<n>STATUS bit assignments Reserved BLKID Reserved IERR SERR Reserved Reserved Reserved Reserved Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 182 of 268...
  • Page 183 Architecturally defined primary error code. RO in error record 0, Returns information shown in Table 5-51: GICT_ERR<n>MISC0.Data field encoding on page otherwise RW 155. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 183 of 268...

  • Page 184: Fmu_Errgsr, Error Group Status Register

    This register receives the unlock key that is required for writes to FMU registers to be successful. This register reads as 0 if the FMU register file is locked. Configurations This register is available in all configurations. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 184 of 268...

  • Page 185: Fmu_Pingctlr, Ping Control Register

    5.10 FMU register summary on page 179 for the address offset, type, and reset value of this register. Usage constraints Only accessible by Secure accesses. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 185 of 268...

  • Page 186: Fmu_Pingnow, Ping Now Register

    • After a write to this register, poll FMU_STATUS.idle to ensure that the effect of the write is complete. • Do not write to FMU_PINGNOW that corresponds to a powered-off block. See Power management on page 208. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 186 of 268...

  • Page 187: Fmu_Smen, Safety Mechanism Enable Register

    • BLK = ITS, SMID = 0 • BLK = SPI Collator, SMID = 0 • BLK = Wake Request, SMID = 0 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 187 of 268...
  • Page 188 Reserved, RAZ [15:8] Block identifier. Table 6-1: Error record block IDs on page 198 for block ID encodings. [7:1] Reserved, RAZ Safety Mechanism enable Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 188 of 268...

  • Page 189: Fmu_Sminjerr, Safety Mechanism Inject Error Register

    [23:16] - Reserved, RAZ [15:8] Block identifier. Table 6-1: Error record block IDs on page 198 for block ID encodings. [7:0] Reserved, RAZ Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 189 of 268...

  • Page 190: Fmu_Pingmask, Ping Mask Register

    For unpopulated GIC blocks, corresponding bits have no effect. The same applies to bit[0], because the FMU does not ping GICD. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 190 of 268...

  • Page 191: Fmu_Status, Fmu Status Register

    Width 32-bit Functional group See 5.10 FMU register summary on page 179 for the address offset, type, and reset value of this register. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 191 of 268...
  • Page 192 Table 5-86: FMU_ERRIDR bit descriptions Bits Name Description [31:16] - Reserved, RAZ [15:0] NUM Highest numbered index of the error records in this group + 1 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 192 of 268...

  • Page 193: Functional Safety

    GIC-600 and do not alter the original GIC-600 functionality. The following figure shows where the main Safety Mechanisms of GIC-600AE reside. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 193 of 268...
  • Page 194 The AXI4-Stream interconnect that connects the GIC blocks, is protected by end-to-end partial duplication. Partial duplication means that the primary interconnect is duplicated with Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 194 of 268...
  • Page 195 Safety Island through the APB port. The APB port is added for FuSa purposes and does not exist on the GIC-600, the non-FuSa version. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 195 of 268...

  • Page 196: Fault Management Unit

    The following figure shows the FMU and its interconnections. Figure 6-2: FMU interconnections GICD Error records APB4 interface fmu_err_int fmu_err_in fmu_fault_int AXI4-Stream interface Interconnect PPI0 PPI1 ITS0 fmu_err_out fmu_err_out fmu_err_out Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 196 of 268...

  • Page 197: Fmu Apb4 Interface

    Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 198: Error Record Format

    ITS2 ITS3 ITS4 ITS5 ITS6 ITS7 PPI0 PPI1 PPI2 PPI3 PPI4 PPI5 PPI6 PPI7 PPI8 PPI9 PPI10 PPI11 PPI12 PPI13 PPI14 PPI15 PPI16 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 198 of 268...

  • Page 199: Fmu Reset

    Table 6-2: Safety Mechanism IDs GIC block Safety Mechanism ID Description GICD Reserved GICD dual lock-step error GICD ACE-Lite subordinate interface error GICD→PPI AXI4-Stream interface error Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 199 of 268...
  • Page 200 PPI→CPU interface AXI4-Stream interface error PPI Q-Channel interface error PPI RAM DED error PPI RAM address decode error PPI RAM SEC error PPI User0 SM Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 200 of 268...
  • Page 201 If repeat reads of IERR always return SMID:0, then it might indicate that the AXI4-Stream interconnect is broken, possibly due to a permanent fault, and is unable to receive Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 202 By introducing error through the software, the error injection feature can be used to test the software error recovery handler. The ClkGate override Safety Mechanisms do not support error injection. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 202 of 268...

  • Page 203: Ping Mechanisms

    The following figure shows the relationship between the ping mechanism parameters. Figure 6-3: Ping mechanism parameters ping_interval ping_interval Ping sent Ping sent Ping sent to PPI0 to PPI1 to ITS0 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 203 of 268...
  • Page 204 Using this method can be helpful to debug PING_ACK violations that background pings cause. The procedure to initiate a directed software ping is as follows: Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 204 of 268...
  • Page 205 GIC block on the remote GIC block to the GICD interface. The receiving GICD block and the ADB, if present, detect the erroneous payload and report it as a fault. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 206: Lock And Key Mechanism

    This behavior is permitted to allow for the case when the APB interconnect splits a single 64-bit register access and presents it to the FMU in any order. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 207: Correctable Error Enable

    If more than one error has been reported by this block to this error record, FMU_ERR<M>STATUS.OF is asserted. In case of overflow, the error record retains the Safety Mechanism ID of the first error. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 207 of 268...
  • Page 208 FMU. Writing to the following registers generates messages to the remote GIC block: • FMU_ERR<n>STATUS • FMU_PINGNOW • FMU_SMEN • FMU_SMINJERR Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 208 of 268...

  • Page 209: Fusa Programmer's View

    Redundant dgb_reset_n reset signal for PMU and FMU. Both resets must assert domain together. dftrstdisable_fdc Input All domains Prevents reset from asserting when reset generation FDC flops are scanned Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 209 of 268...

  • Page 210: P-Channel And Q-Channel Fusa Ports

    Redundant clkqactive port clkqacceptn_chk Output Redundant clkqacceptn port clkqdeny_chk Output Redundant clkqdeny port preq_chk Input P-Channel device interface for the GICD block Redundant preq port Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 210 of 268...

  • Page 211: Amba Interface Fusa Ports

    6.10 P-Channel and Q-Channel protection on page 232 for more information. 6.4.3 AMBA interface FuSa ports The following interfaces add the parity extended chk signal bits, as specified in the Arm AMBA ® Parity Extensions. In the following table, Granularity refers to the hierarchy or the block in which the ports are relevant.

  • Page 212: Clocks

    The clocks that are used for wrap components are: This signal clocks the primary mission-critical logic clk_fdc This signal clocks the Fault Detection and Control (FDC) redundant logic Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 212 of 268...
  • Page 213 213, the architecturally gated clocks are the clk_dn and clk_ppsgi signals. On the redundant side, the clk_fdc signal works similarly but uses its own redundant cells. ClkGate Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 213 of 268...

  • Page 214: Resets

    It also filters out transient reset assertion by preventing reset from propagating unless the reset_n and reset_n_fdc signals are both asserted. The following figure shows this behavior in a timing diagram. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 214 of 268...
  • Page 215 Internal reset fault protection/detection The reset trees are duplicated, so faults on reset trees are detected through lockstep protection mechanisms for the affected blocks. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 215 of 268...
  • Page 216 To assert the dbg_reset_n_sync and dbg_reset_n_fdc_sync signals, both external ports must be asserted. 2. Keep the resets asserted for 16 clk cycles. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 216 of 268...

  • Page 217: Lock-Step Protection

    • The RAMs, which are shared • The internal AXI4-Stream interconnect, which uses full duplication The following figure shows the lock-step for the PPI (Redistributor). Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 217 of 268...

  • Page 218: Comparators

    • Prevent flagging on benign glitches when nothing is reading the bus. • Prevent a false error from being asserted due to unknown values on the bus, from RAMs, or from uninitialized datapath flops. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 218 of 268...

  • Page 219: Non-Resettable Flops

    The GIC-600AE inherits SECDED ECC protection and patrol scrubbing from GIC-600. The address is not protected on GIC-600, so this protection is added on GIC-600AE. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 219 of 268...

  • Page 220: Secded Ecc Data Protection

    Common Mode Failure (CMF). This protection is achieved by calculating parity for the address bits and writing the parity into the RAM along with the data. The following figure shows how the address protection works. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 220 of 268...

  • Page 221: Ram Scrubbing

    These external interfaces include: • ACE-Lite • APB • AXI4-Stream, and the following interfaces, which use AXI4-Stream as their transport: ◦ GIC Stream Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 221 of 268...

  • Page 222: Ace-Lite Interface Parity Protection

    If this protection is not needed, software can disable the appropriate ACE-Lite Safety Mechanisms by programming the FMU_SMEN register. Disable this protection when using an interconnect that does not generate AMBA ® parity. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 222 of 268...
  • Page 223 4-12 arvalid==1 arctlchk2 ardomain, arsnoop, arbar arvalid==1 awatop is used for atomics, and is only visible when atomic_support==1 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 223 of 268...

  • Page 224: Axi4-Stream Interface Parity Protection

    Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 224 of 268...

  • Page 225: Apb Interface Parity Protection

    8 psel&&pwrite preadychk pready penable==1 prdatachk prdata ceil(DataWidth/8) 8 psel&&pready&&!pwrite pslverrchk pslverr pready Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 225 of 268...

  • Page 226: Axi4-Stream Internal Interconnect Protection

    • The wide orange line represents the primary interconnect and payload • The narrow orange line represents the redundant interconnect compressed and represented by Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 226 of 268...
  • Page 227 • Two cycles ahead of the shadow, which is the normal case • Three cycles ahead of the shadow, which is a slow shadow Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 227 of 268...

  • Page 228: Non-Gic Interconnect Ip

    flags a fault if there is a mismatch. If the parity protection is not needed, tie off the extra parity inputs and program the GIC-600AE to disable this protection. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 228 of 268...
  • Page 229 Before you begin Configure and render your non-GIC interconnect, as 6.9.2.1 Configuring and integrating with a non-GIC interconnect on page 228 describes. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 229 of 268...
  • Page 230 Table 6-11: Mandatory fmu_err_out signal connections for a non-GIC-rendered interconnect fmu_err_in[x] && block ID Block GICD SPI Collator Wake Request Reserved ITS0 ITS1 ITS2 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 230 of 268...
  • Page 231 There are some fault_* signals that are used only by a GIC rendered interconnect. Therefore, if a non-GIC rendered interconnect is used, those fault_* signals must be tied off. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 232: P-Channel And Q-Channel Protection

    The P-Channel and Q-Channel logic and connections can be complex for topologies with multiple clock or power domains. The following figure shows a top-level example of a GIC topology with multiple clock domains. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 232 of 268...
  • Page 233 CPUIF CPUIF CPUIF CPUIF CORE CORE CORE CORE The following figure shows a top-level example of a GIC topology with multiple power domains. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 233 of 268...
  • Page 234 GIC rendering engine. The GIC uses a Q-Channel for power control in all cases except for cross/remote chip power control, which uses a P-Channel port on the Distributor. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 235: Chk Bit Timing

    The skew of the preqn, preqn_chk, qreqn, and qreqn_chk signals must be less than the maximum skew that the SAF detection logic allows. Clock Ratio (CR) Equal to (GIC clock frequency) / (channel controller clock frequency). Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 235 of 268...

  • Page 236: Transient Faults

    Figure 6-15: Normal assertion of qreqn and qreqn_chk signals QREQn QREQn_chk QREQn_int Count Error The following figure shows how a transient fault on the qreqn signal is filtered. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 236 of 268...
  • Page 237 If it detects a polarity difference between the qreqn and qreqn_chk signals, it starts counting down. If the counter reaches zero, it flags an error. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 237 of 268...

  • Page 238: Stuck-At Faults

    The following figure shows how the SAF detector detects a stuck-at-one error on the qreqn_chk signal. Figure 6-19: Stuck-at-one error on qreqn_chk signal QREQn QREQn_chk QREQn_int Count Error Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 238 of 268...

  • Page 239: Disabling P-Channel And Q-Channel Safety Mechanisms

    Except for the pstate signal, each P-Channel signal bit has a corresponding chk signal bit with inverted polarity. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 239 of 268...
  • Page 240 State 000 State 001 PSTATECHK PREQ PREQCHK PACCEPT PACCEPTCHK PDENY PDENYCHK Power Pre-Transition Actions Post-Transition Actions Controller Actions P_STABLE P_REQUEST P_ACCEPT P_COMPLETE P_STABLE Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 240 of 268...

  • Page 241: Q-Channel

    PDENY PDENYCHK Power Pre-Transition Actions Post-Transition Actions Controller Actions P_STABLE P_REQUEST P_ACCEPT P_COMPLETE P_STABLE 6.10.6 Q-Channel This section contains information for Q-Channel protection. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 241 of 268...
  • Page 242 Each Q-Channel signal bit has a corresponding chk signal bit with inverted polarity. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 242 of 268...
  • Page 243 The following figure shows the opposite polarity of the chk signal bits during the Q-Channel denial sequence. Figure 6-25: Q-Channel denial qreqn qreqnchk qacceptn qacceptnchk qdeny qdenychk Q_RUN Q_REQUEST Q_DENIED Q_CONTINUE Q_RUN Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 243 of 268...

  • Page 244: Ppi And Spi Interrupt Interface Protection

    Implementation skew Silicon skew due to asynchronous clock domain crossings or other factors Temporal delay skew Skew between lock-step primary and redundant logic blocks Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 244 of 268...

  • Page 245: Ppi And Spi Transient Faults

    The following figure shows an assertion of an spi signal that causes a transient fault. Figure 6-27: Transient fault on spi spi_chk spi_int Count Error Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 245 of 268...

  • Page 246: Ppi And Spi Stuck-At Faults

    The following parameters apply to PPI and SPI interrupt interface protection. • fusa_spi_prot • fusa_ppi_prot For more information about these parameters, see Configuration options in the Arm ® CoreLink ™ GIC-600AE Generic Interrupt Controller Configuration and Integration Manual. 6.12 Systematic fault watchdog protection The GIC-600AE contains a watchdog-based PING/ACK mechanism that guards against systematic errors on the interconnect.

  • Page 247: Dft Protection

    If faults occur on the MBIST controller or MBIST signals, it is assumed the MBIST controller detects them. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 247 of 268...

  • Page 248: Atpg/Scan

    Scan enable 6.13.3 LBIST Arm has verified that a third-party LBIST controller can be instanced and used to control the scan chains and obtain additional latent fault coverage or diagnostic information. 6.14 Generic fault inputs Each GIC block has generic fault inputs that allow the SoC integrator to connect and flag external faults through the FMU.

  • Page 249: Configuration And Parameters

    Mechanisms. For more information, see 6.10.4 Disabling P-Channel and Q-Channel Safety Mechanisms page 238. For more information about these parameters, see the Configuration options chapter of the Arm ® CoreLink ™ GIC-600AE Generic Interrupt Controller Configuration and Integration Manual.

  • Page 250: Signal Descriptions

    Write control (mbistwriteen) and read control (mbistreaden). No access occurs if both enables are LOW. It is illegal to activate both enables simultaneously. [<domain>_]mbistreaden Input The variable is configuration-dependent. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 250 of 268...

  • Page 251: Power Control Signals

    The its_count parameter sets the number of ITS blocks on the chip. qactive_its[<its>] Output These signals are not present in monolithic configurations where the Distributor and ITS share an ACE-Lite port. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 251 of 268...
  • Page 252 Q-Channel device interface for the CoreLink ™ ADB-400 AMBA ® Domain Bridge power interface within the domain. [<domain_>]pwrqacceptn Output [<domain_>]pwrqdeny Output [<domain_>]pwrqactive Output Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 252 of 268...

  • Page 253: Interrupt Signals

    SPI output after synchronization and edge detection. Can be used for cross-domain The spi_wire configuration pulse detection. parameter controls the number of SPIs. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 253 of 268...

  • Page 254: Cpu Interface Signals

    Registered wake signal to indicate that a message is arriving or is about to arrive on the IRI bus of the [_<bus>] cluster Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 254 of 268...

  • Page 255: Ace-Lite Interface Signals

    This signal indicates that the channel is signaling a valid write response. bready_[its[_<num>]]_s Input This signal indicates that the manager can accept a write response. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 255 of 268...
  • Page 256 This signal indicates that the manager can accept the read data and response information. ruser_[its[_<num>]]_s[n:0] Output Read response User signal, where n = axis_ruser_width−1 The variable is configuration-dependent. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 256 of 268...
  • Page 257 This signal indicates that the channel is signaling a valid write response. bresp_[its[_<num>]]_m[1:0] Input This signal indicates the status of the write transaction. buser_[its[_<num>]]_m[n:0] Input Write response User signal, where n = axis_buser_width−1 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 257 of 268...

  • Page 258: Miscellaneous Signals

    An ID number that identifies the Redistributor in the system. Software can read the GICR_CFGID0 register to access the value of this signal. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 258 of 268...
  • Page 259 GITS_TRANSLATER. The value is ignored for non-MSI writes. See 3.4 MSI-64 Encapsulator on page 40 and 3.4.1 MSI-64 ACE-Lite interfaces on page 40. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 259 of 268...

  • Page 260: Interblock Axi4-Stream Interface Signals

    Indicates the data bytes that must be transferred. This signal is only present on the Distributor. icditdest[variable:0] Output Specifies the destination ITS block. This signal is only present on the Distributor. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 260 of 268...
  • Page 261 Registered wake signal to indicate that a message is arriving or is about to arrive on the iccd bus iccdtid Output Indicates the SPI Collator number. This signal is only present on the Distributor, and must be set LOW. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 261 of 268...

  • Page 262: Interdomain Signals

    Registered wake signal to indicate that a message is arriving or is about to arrive on the icrd bus. The icrdtvalid and icrdtready signals control data transfer. Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 263: Implementation-Defined Features

    All implemented SPIs, SGIs, and PPIs have programmable groups. grouping interrupt grouping handling and prioritization Interrupt Physical Enabling All SGIs have a programmable enable. enables interrupt individual handling and interrupts prioritization Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 263 of 268...
  • Page 264 See the ® Generic Interrupt Controller Architecture Specification, GIC tables specific tables architecture version 3 and version 4 peripheral interrupts and the ITS Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 264 of 268...

  • Page 265: Revisions

    3.3 Interrupt Translation Service on page 34 Updated the ACE_LITE_ACCESS_FAILURE 4.15.6.7 ITS command and translation error records 13 and description beyond on page 81 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 265 of 268...
  • Page 266 Added the remote_block_inject_error and gicd_inject_error 5.10.7 FMU_PINGNOW, Ping Now register on page 186 bits Updated the Usage constraints 5.10.10 FMU_PINGMASK, Ping Mask register on page Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 266 of 268...
  • Page 267 Identification Register on page 103 • 5.4.1 GICR_IIDR, Redistributor Implementation Identification Register page 122 • 5.6.1 GITS_IIDR, ITS Implementer Identification Register on page 138 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 267 of 268...
  • Page 268 Deleted the “must not backpressure” text • A.7 Interblock AXI4-Stream interface signals on page 259 • A.9 Interchip AXI4-Stream interface signals on page 262 Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 268 of 268...

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