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ARM CoreLink GFC-200 Technical Reference Manual

Generic flash controller
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Arm
CoreLink™ GFC-200 Generic Flash Controller
®
Revision: r0p0
Technical Reference Manual
Non-Confidential
Copyright © 2019, 2022 Arm Limited (or its affiliates).
All rights reserved.
Issue 01
101484_0000_01_en

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  • Page 1 CoreLink™ GFC-200 Generic Flash Controller ® Revision: r0p0 Technical Reference Manual Non-Confidential Issue 01 101484_0000_01_en Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved.
  • Page 2 No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.
  • Page 3 Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company.
  • Page 4 Technical Reference Manual Inclusive language commitment Arm values inclusive communities. Arm recognizes that we and our industry have used language that can be offensive. Arm strives to lead the industry and create change. Previous issues of this document included language that can be offensive. We have replaced this language.

  • Page 5: Table Of Contents

    3.2.9 Partition configuration interface......................25 3.2.10 System interface............................. 27 3.3 Clocking................................28 3.4 Resets................................28 3.5 Interrupt sources............................28 3.6 Generic Flash Bus arbiter...........................30 3.7 Flash power control............................. 31 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 5 of 90...
  • Page 6 4.4.26 Peripheral ID register 2, PIDR2......................69 4.4.27 Peripheral ID register 3, PIDR3......................70 4.4.28 Component ID register 0, CIDR0.......................71 4.4.29 Component ID register 1, CIDR1.......................71 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 6 of 90...
  • Page 7 A.5 GFB manager interface signals......................... 86 A.6 Partition control interface signals......................87 A.7 Q-Channel interface signals........................88 A.8 P-Channel controller interface signals.....................89 A.9 DFT signals..............................89 B Revisions................................90 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 7 of 90...

  • Page 8: Introduction

    ® Glossary is a list of terms used in Arm documentation, together with definitions for those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning. See the Arm Glossary for more information: developer.arm.com/glossary.
  • Page 9 The actual level is unimportant and does not affect normal operation. Figure 1-1: Key to timing diagram conventions Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 9 of 90...

  • Page 10: Additional Reading

    JEP106 JEDEC Standard Manufacturer’s Identification Code Arm tests its PDFs only in Adobe Acrobat and Acrobat Reader. Arm cannot guarantee the quality of its documents when used with any other PDF reader. Adobe PDF reader products can be downloaded at http:/ /www.adobe.com...

  • Page 11: Overview

    Generic Flash Bus (GFB) supplied with GFC-200. The following figure shows how the GFC-200 is used in a Flash controller implementation. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 11 of 90...

  • Page 12: Compliance

    The GFC-200 interfaces are compliant with Arm specifications and protocols. The GFC-200 is compliant with the: • AMBA GFB protocol. See the AMBA Generic Flash Bus Protocol Specification. ® ® Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 12 of 90...

  • Page 13: Features

    • Interrupt capability for long running commands • Access to internal registers APB register requester interface: • Enables access to the registers in the process-specific part Q-Channel interface: Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 13 of 90...

  • Page 14: Configurable Options

    For relevant protocol and architectural information that relates to this product, see 1.4 Additional reading on page 10". The GFC-200 documentation is as follows: Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 14 of 90...

  • Page 15: Product Revisions

    • How to implement GFC-200 into your design. • The processes to validate the configured design. The Arm product deliverables include reference scripts and information about using them to implement your design. The CIM is a confidential book that is only available to licensees.

  • Page 16: Functional Description

    GFC-200 comprises several submodules. The following figure shows the internal high-level structure of an example system that integrates GFC-200 with a process-specific part and embedded Flash. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 16 of 90...

  • Page 17: Interfaces

    3.2 Interfaces GFC-200 has several interfaces that enable it to communicate with the system and the process- specific part. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 17 of 90...

  • Page 18: Ahb-Lite Subordinate Interface

    4MB, then aliasing might occur in the process-specific part. Therefore, the process-specific controller must provide protection against aliasing, so that it can give an error response for any out- of-range addresses. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 18 of 90...
  • Page 19 • If the secondary AHB manager (hpart == 1) initiates an access, while the GFC-200 is in partition configuration mode. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 19 of 90...

  • Page 20: Primary Apb Completer Interface

    Therefore, any errors that the APB requester interface receives, are forwarded through the APB completer interface to the access initiator. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 20 of 90...

  • Page 21: Secondary Apb Completer Interface

    HIGH, it sets the GFC-200 qactive outputs HIGH to generate a wake request to the system Q-Channel controllers. Related information APB completer interface signals on page 83 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 21 of 90...

  • Page 22: Apb Requester Interface

    The GFC-200 allows access to a 4MB memory region. Data width The configuration parameters set the width of the read data bus FRDATA_WIDTH FWDATA_WIDTH and the write data bus, respectively. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 22 of 90...
  • Page 23 • For more information about GFB transactions, see the AMBA Generic Flash Bus ® Protocol Specification. Related information Control register, CTRL on page 47 GFB manager interface signals on page 86 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 23 of 90...

  • Page 24: Q-Channel Interface For Clock

    When the PPU requests power to be disabled, if there is any ongoing activity in the GFC-200 then it denies the request. Related information Q-Channel interface signals on page 88 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 24 of 90...

  • Page 25: P-Channel Controller Interface

    Each bit sets the domain owner of the corresponding partition. By default, the owner has read/write access to that partition. For example, if: Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 25 of 90...
  • Page 26 The GFC-200 has an config_mode_me_en input signal. When the GFC-200 is in configuration mode, the primary domain can use config_mode_me_en to initiate a MASS ERASE operation, regardless of the partition assignment. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 26 of 90...

  • Page 27: System Interface

    3.7 Flash power control on page 30 for more information about Flash power modes and OPMODEs. Related information System interface signals on page 82 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 27 of 90...

  • Page 28: Clocking

    1. The IRQ_ENABLE_SET.CMD_ACCEPT_IRQ_EN_SET bit controls whether the relevant irq signal goes HIGH when CMD_ACCEPT_IRQ is set to 1. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 28 of 90...
  • Page 29 The GFC-200 sets PWR_STATE_CHANGE_IRQ to 1, when the power state of the Flash memory changes. The IRQ_ENABLE_SET.PWR_STATE_CHANGE_IRQ_EN_SET bit controls whether the relevant irq signal goes HIGH when PWR_STATE_CHANGE_IRQ is set to 1. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 29 of 90...

  • Page 30: Generic Flash Bus Arbiter

    After arbitration, the GFC-200 performs access control on Flash requests based on the partition access rights configuration. Only those accesses that target a permitted partition are forwarded to the GFB. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 30 of 90...

  • Page 31: Flash Power Control

    FUNC_RET (OPMODE_0) Sleep 0b0_0111 0b1_0101 FULL_RET (OPMODE_1) Powerdown (low-voltage read mode) 0b0_0101 FULL_RET (OPMODE_0) Powerdown OFF (OPMODE_1) All power off 0b1_0000 OFF (OPMODE_0) 0b0_0000 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 31 of 90...

  • Page 32: Programmers Model

    • AHB-Lite subordinate interface, 4MB. • GFB, 4MB. • APB primary completer interface, 8KB. • APB secondary completer interface, 4KB. • APB requester interface, 4KB. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 32 of 90...

  • Page 33: Ahb Subordinate Interface Memory Map

    The GFC-200 supports both read and write, or erase. • § Access rights also depend on the partition control signals. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 33 of 90...
  • Page 34 4MB address space of the Flash area. For any out-of-range addresses, Arm expects the process-specific part to respond with error. The example memory map has 256 pages in the main memory area. GFC-200 maps 4MB of address space from the system memory to the GFB address range.
  • Page 35 For this example, the partition control input signals are: • partition_ctrl_rw[15:0] == 0xFFFC • partition_ctrl_rd[15:0] == partition_ctr_rw[15:0] Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 35 of 90...
  • Page 36 For this example, the partition control input signals are: • partition_ctrl_rw[15:0] == 0x0006 • partition_ctrl_rd[15:0] == partition_ctr_rw[15:0] Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 36 of 90...
  • Page 37 For this example, the partition control input signals are: • partition_ctrl_rw[n] == 0b1 • partition_ctrl_rd[n] == 0b0 • partition_ctrl_ro[n] == 0b0 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 37 of 90...

  • Page 38: Apb Memory Maps

    APB 0 interface, is that the GFC-200 is aware of any quiescence requests and can block access to the process-specific part. The secondary domain cannot access the process-specific part registers but it can access the GFC-200 registers. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 38 of 90...

  • Page 39: Register Summary

    ACCESS_ERR_RESP_CTRL on page 60 A signal or configuration parameters set the reset value of this register. See the register description for more information. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 39 of 90...

  • Page 40: Register Descriptions

    The IRQ_ENABLE_SET register characteristics are: Usage constraints Setting a bit to zero has no effect. Bits[7:6] functionality is accessible to the primary requester only. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 40 of 90...
  • Page 41 Set to 1 to enable the CMD_FAIL_IRQ bit to generate interrupts on the interrupt signal, irq0 or irq1, that belongs to the APB requester. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 41 of 90...

  • Page 42: Interrupt Enable Clear Register, Irq_Enable_Clr

    8 7 6 5 4 3 2 1 0 Reserved ACC_VIOLATION_IRQ_EN_CLR CMD_ACCEPT_IRQ_EN_CLR PART_CONFIG_MODE_IRQ_EN_CLR CMD_SUCCESS_IRQ_EN_CLR POWER_STATE_CHANGE_IRQ_EN_CLR CMD_FAIL_IRQ_EN_CLR CMD_REJECT_IRQ_EN_CLR READ_OVERFLOW_IRQ_EN_CLR The following table shows the register bit assignments. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 42 of 90...

  • Page 43: Interrupt Status Set Register, Irq_Status_Set

    Bits[7:6] functionality is accessible to the primary requester only. Configurations Available in all configurations. Each APB interface has its own instance of an IRQ_STATUS_SET register. Attributes Offset 0x008 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 43 of 90...
  • Page 44 The IRQ_MASKED_STATUS also provides the status of the interrupt bits. However, the values that IRQ_MASKED_STATUS returns might differ from the IRQ_STATUS_SET value, because the IRQ_MASKED_STATUS value depends on whether an interrupt is enabled. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 44 of 90...

  • Page 45: Interrupt Status Clear Register, Irq_Status_Clr

    ACC_VIOLATION_IRQ_STS_CLR Set to 1 to clear the ACC_VIOLATION_IRQ bit to 0. For the secondary requester, this bit is reserved and behaves as RAZ/WI. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 45 of 90...

  • Page 46: Interrupt Masked Status Register, Irq_Masked_Status

    Available in all configurations. Each APB interface has its own instance of an IRQ_MASKED_STATUS register. Attributes Offset 0x010 Type Read only. Reset Width The following figure shows the bit assignments. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 46 of 90...

  • Page 47: Control Register, Ctrl

    There are no usage constraints. Configurations Available in all configurations. Each APB interface has its own instance of a CTRL register. Attributes Offset 0x014 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 47 of 90...
  • Page 48 When the GFC-200 accepts a command, it clears the CMD field to 0b000 and sets STATUS.CMD_ACCEPT = 1. Reading the CMD field shows the pending GFB command. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...

  • Page 49: Status Register, Status

    CMD_PENDING CMD_ACCEPT CMD_SUCCESS CMD_FAIL CMD_FINISH ARBITRATION_LOCKED The following table shows the register bit assignments. Table 4-8: STATUS Bits Name Function [31:6] - Reserved. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 49 of 90...

  • Page 50: Address Register, Addr

    The value that is written to the ADDR field must be either: • 32-bit aligned for write accesses to the embedded Flash. • 128-bit aligned for read accesses from the embedded Flash. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 50 of 90...

  • Page 51: Data 0 Register, Data0

    There are no usage constraints. Configurations Available in all configurations. Each APB interface has its own instance of a DATA0 register. Attributes Offset 0x020 Type Read/write Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 51 of 90...

  • Page 52: Data 1 Register, Data1

    > 32. When present, each APB interface has FWDATA_WIDTH its own instance of a DATA1 register. Attributes Offset 0x024 Type Read/write Reset Width The following figure shows the bit assignments. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 52 of 90...

  • Page 53: Data 2 Register, Data2

    Width The following figure shows the bit assignments. Figure 4-16: DATA2 register bit assignments DATA2 The following table shows the register bit assignments. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 53 of 90...

  • Page 54: Data 3 Register, Data3

    For reads from the embedded Flash, this field returns the read data bits[127:96]. For writes to the embedded Flash, this field contains the write data bits[127:96]. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 54 of 90...

  • Page 55: Partition Ownership Status Register, Part_Ctrl_Rw_Status

    Note: The owner of a partition has read/write access to that partition unless the PART_CTRL_RO_STATUS register indicates that the partition is read only. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 55 of 90...

  • Page 56: Partition Control Read-Only Status Register, Part_Ctrl_Ro_Status

    Partition x is not read only, so the owner of the partition has read/write access. Bit[x] == 1 Partition x is read only. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 56 of 90...

  • Page 57: Partition Control Read Status Register, Part_Ctrl_Rd_Status

    Therefore, only the owner of the partition has access to partition x. Bit[x] == 1 The system enables the non-owner of a partition to read partition x. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 57 of 90...

  • Page 58: Partition Configuration Mode Request Register, Part_Config_Mode_Req

    HIGH. When software services the interrupt, it must clear the interrupt by setting IRQ_STATUS_CLR.PART_CONFIG_MODE_IRQ_STS_CLR = 1. Set to 0, to request that the GFC-200 exits partition configuration mode. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 58 of 90...

  • Page 59: Partition Configuration Mode Status Register, Part_Config_Mode_Status

    Figure 4-22: PART_CONFIG_MODE_STATUS register bit assignments Reserved PART_CONFIG_MODE_STATUS The following table shows the register bit assignments. Table 4-18: PART_CONFIG_MODE_STATUS Bits Name Function [31:1] Reserved. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 59 of 90...

  • Page 60: Access Violation Response Register, Access_Err_Resp_Ctrl

    Figure 4-23: ACCESS_ERR_RESP_CTRL register bit assignments Reserved ACCESS_ERR_RESP_CTRL The following table shows the register bit assignments. Table 4-19: ACCESS_ERR_RESP_CTRL Bits Name Function [31:1] - Reserved. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 60 of 90...

  • Page 61: Access Violation Response Register, Access_Err_Info

    Available in all configurations. This register is present in the primary APB interface register space only. Attributes Offset 0x04C Type Read only. Reset 0x0. Width The following figure shows the bit assignments. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 61 of 90...

  • Page 62: Power State Status Register, Power_State

    The following figure shows the bit assignments. Figure 4-25: POWER_STATE register bit assignments POWER Reserved _STATE NON_LV_MODE The following table shows the register bit assignments. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 62 of 90...

  • Page 63: Power State Request Register, Power_State_Req

    Available in all configurations. Each APB interface has its own instance of a POWER_STATE_REQ register. Attributes Offset 0x054 Type Read/write. Reset 0x8. Width The following figure shows the bit assignments. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 63 of 90...

  • Page 64: Hardware Parameters Register, Hwparams

    AHB interfaces, and the size of the Flash partition. The HWPARAMS register characteristics are: Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes Offset 0x060 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 64 of 90...
  • Page 65 0b0011111 == 32-bit GFB read data bus width. 0b0111111 == 64-bit GFB read data bus width. 0b1111111 == 128-bit GFB read data bus width. Reserved, returns 0. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 65 of 90...

  • Page 66: Peripheral Id Register 4, Pidr4

    Figure 4-28: PIDR4 register bit assignments Reserved SIZE DES_2 The following table shows the register bit assignments. Table 4-24: PIDR4 Bits Name Function [31:8] - Reserved, returns 0. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 66 of 90...

  • Page 67: Peripheral Id Register 0, Pidr0

    Returns 0, which indicates that the GFC-200 registers occupy a single 4KB page. [3:0] DES_0 Indicates how many Continuation Codes (0x7F) an Arm device requires. For identifying an Arm device or product, the Standard Manufacturer’s Identification Code specifies a requirement of four Continuation Codes.

  • Page 68: Peripheral Id Register 1, Pidr1

    Reserved, returns 0. [7:4] DES_0 The JEDEC JEP106 ID code [3:0], which identifies Arm as the designer of the GFC-200. See also PIDR2.DES_1 and the Standard Manufacturer’s Identification Code. [3:0] PART_1 Part number, bits[11:8], for the GFC-200. See also PIDR0.PART_0. The GFC-200 part number is 833.

  • Page 69: Peripheral Id Register 2, Pidr2

    Returns 1, which indicates the use of a JEDEC-assigned ID value. [2:0] DES_1 The JEDEC JEP106 ID code [6:4], which identifies Arm as the designer of the GFC-200. See also PIDR1.DES_0[3:0] and the Standard Manufacturer’s Identification Code. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved.

  • Page 70: Peripheral Id Register 3, Pidr3

    Function [31:8] - Reserved, returns 0. [7:4] REVAND A nonzero value indicates that Arm has approved the application of a post-manufacture metal layer fix to the GFC-200 silicon. [3:0] CMOD Customer modification number. A nonzero value indicates that the customer has modified the GFC-200 RTL, which might affect its behavior.

  • Page 71: Component Id Register 0, Cidr0

    ID to discover that the peripheral contains a programmers register block and which component class the GFC-200 belongs to. The CIDR1 register characteristics are: Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 71 of 90...

  • Page 72: Component Id Register 2, Cidr2

    ID to discover that the peripheral contains a programmers register block. The CIDR2 register characteristics are: Usage constraints There are no usage constraints. Configurations Available in all configurations. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 72 of 90...

  • Page 73: Component Id Register 3, Cidr3

    The CIDR3 register characteristics are: Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes Offset 0xFFC Type Read only. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 73 of 90...

  • Page 74: Accessing Flash From The Apb Completer Interfaces

    Software must follow a particular flow to access the embedded Flash from the APB completer interfaces. The following figure shows how to access the embedded Flash from an APB completer interface. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 74 of 90...
  • Page 75 The APB completer interface can use either of two modes to trigger a new command: Polling method Software polls the STATUS register for any active bits, where an active bit indicates that GFC-200 is processing a command. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 75 of 90...

  • Page 76: Preloading Transfers

    Flash transfers back-to-back, and keep the Flash in the high-voltage programming state. The following figure shows the ROW WRITE timing diagram. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 76 of 90...
  • Page 77 Otherwise, the GFC-200 inserts an IDLE command, and software does not get the benefits of the ROW WRITE command. Arm expects the write commands to the embedded Flash to require thousands of clock cycles, so software can use this period to service the CMD_ACCEPT_IRQ interrupt and update the registers.
  • Page 78 Document ID: 101484_0000_01_en ® CoreLink™ GFC-200 Generic Flash Controller Issue: 01 Technical Reference Manual Programmers Model The following figure shows the ROW WRITE preloading flowchart. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 78 of 90...
  • Page 79 Wait CMD_SUCCESS_IRQ This writes address n Write ADDR register or CMD_FAIL_IRQ Clear CMD_SUCCESS_IRQ Write DATA register or CMD_FAIL_IRQ Write CTRL register ROW WRITE finished Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 79 of 90...

  • Page 80: Reconfiguring The Partition Access Rights

    ERROR response and it sets CMD_FAIL_IRQ = 1. If the secondary domain issues an APB command, then the GFC-200 sets CMD_FAIL_IRQ = 1. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 80 of 90...

  • Page 81: Flash Macro Power Control

    POWER_STATE_REQ registers. If a domain does not have any requirements to access Flash, then Arm recommends that its POWER_STATE_REQ register is set to all zeros so that the other domain can control the Flash power requirements.

  • Page 82: A Signal Descriptions

    The transfers that the GFC-200 receives are forwarded to the GFB interface. The following table shows the AHB-Lite subordinate interface signals. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 82 of 90...
  • Page 83 AHB-Lite signals that are not shown in the table are not used in GFC-200. See the AMBA ® 3 AHB‑Lite Protocol Specification v1.0 for more information. Related information AHB-Lite subordinate interface on page 17 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 83 of 90...

  • Page 84: Apb Completer Interface Signals

    Input Address bus. pstrb_s1[3:0] Write strobe port. Each bit refers to a byte in the pwdata_s1 signal. Input pwrite_s1 Input APB transfer direction. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 84 of 90...

  • Page 85: Apb Requester Interface Signals

    APB signals that are not shown in the table are not used in GFC-200. See the AMBA ® APB Protocol Specification Version 2.0 for more information. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 85 of 90...

  • Page 86: Gfb Manager Interface Signals

    Flash error indication for the previously accepted command. Driven HIGH for two cycles when an error is indicated for the command that is running. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 86 of 90...

  • Page 87: Partition Control Interface Signals

    The owner of partition n has read/write access to that partition. Bit[n] = 1 The owner of partition n has read-only access to that partition. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 87 of 90...

  • Page 88: Q-Channel Interface Signals

    This signal indicates when the GFC-200 is active or it is requesting to exit from quiescence. Related information Q-Channel interface for clock on page 23 Q-Channel interface for power on page 24 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 88 of 90...

  • Page 89: P-Channel Controller Interface Signals

    When HIGH, this signal prevents asynchronous reset signals from resetting the GFC-200 during shift, but allows the logic to be tested completely and at-speed during capture. Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 89 of 90...

  • Page 90: B Revisions

    Table B-2: Differences between issue 0000-00 and issue 0000-01 Change Location Affects Removed offensive terms. Throughout document. All versions Added inclusive language statement. Inclusive language commitment on page 4 Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 90 of 90...

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