ARM Cortex-A9 MBIST Technical Reference Manual

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Cortex

-A9 MBIST Controller

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Revision: r1p0

Technical Reference Manual

ARM DDI 0414C

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Page 2: Change History
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 5: Table Of Contents
About the MBIST instruction register ............3-2 Field descriptions ..................3-4 Chapter 4 MBIST Datalog Register About the MBIST Datalog Register ............. 4-2 Field descriptions ..................4-3 ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 6 Contents Appendix A Signal Descriptions MBIST controller interface signals .............. A-2 Miscellaneous signals ................. A-4 Appendix B Revisions Glossary Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 7 MaxXAddr field encoding ..................3-10 Table 3-8 MaxYAddr field encoding ..................3-10 Table 3-9 ArrayEnables field encoding ................... 3-11 Table 3-10 ColumnWidth field encoding ................... 3-13 ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 8 Miscellaneous signals ....................A-4 Table B-1 Differences between issue A and issue B ..............B-1 Table B-2 Differences between issue B and issue C ..............B-1 viii Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 9 Data in for GHB RAM ....................2-10 Figure 2-14 MBIST controller block .................... 2-11 Figure 2-15 Loading the MBIST controller instruction ..............2-15 Figure 2-16 Starting the MBIST test ................... 2-16 ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 10 Figure 3-1 MBIST instruction register control unit ..............3-2 Figure 3-2 MBIST instruction register dispatch unit ..............3-2 Figure 4-1 MBIST Datalog Register format ................4-2 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 11: Preface
Preface This preface introduces the Cortex-A9 MBIST Controller Technical Reference Manual. It contains the following sections: • About this book on page xii • Feedback on page xvi. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential...
Page 12: About This Book
Identifies the minor revision or modification status of the product. Intended audience This book is written for hardware engineers who are familiar with ARM technology and want to use the MBIST controller to test the RAM blocks used by the Cortex-A9 processor.
Page 13 < and > Enclose replaceable terms for assembler syntax where they appear in code or code fragments. For example: • MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2> ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. xiii Non-Confidential Restricted Access...
Page 14: Key To Timing Diagram Conventions
Denotes Advanced Trace Bus (ATB) flush control signals. Prefix AR Denotes AXI read address channel signals. Prefix AT Denotes ATB data flow signals. Prefix AW Denotes AXI write address channel signals. Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 15 Denotes AXI read data channel signals. Prefix W Denotes AXI write data channel signals. Further reading This section lists publications by ARM and by third parties. for access to ARM documentation. http://infocenter.arm.com ARM publications This book contains information that is specific to this product. See the following documents for other relevant information: •...
Page 16: Feedback
Preface Feedback ARM welcomes feedback on the MBIST controller and on its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier giving: • the product name • The product revision or version.
Page 17: Chapter 1 Introduction
This chapter describes the purpose of the MBIST controller. It contains the following sections: • About the MBIST controller on page 1-2 • MBIST controller interface on page 1-3 • Product revisions on page 1-7. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 18: About The Mbist Controller
Cortex-A9 / controller unit A9MP NORAM CPU2 RAMs (for MP version) CPU3 RAMs (for MP version) SCU RAMs (for MP version) Figure 1-1 Cortex-A9 MBIST configuration Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 19: Mbist Controller Interface
MBISTINDATA[63:0] MBISTWRITEEN MBISTWRITEEN MBIST controller Cortex-A9/A9MP Figure 1-2 MBIST controller wiring diagram Figure 1-3 on page 1-4 shows the traditional method of accessing RAMs for MBIST. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 20: Figure 1-3 Traditional Method Of Interfacing Mbist
Figure 1-4 on page 1-5 shows the six pipeline stages used to access the RAM arrays. Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 21: Figure 1-4 Cortex-A9 Processor Mbist Interface
Functional path MBISTWRITEEN data1 datan MBISTADDR data1 ADDR datan MBISTENABLE MBISTENABLE denotes a D-type flip flop unless otherwise indicated Figure 1-4 Cortex-A9 processor MBIST interface ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 22: Table 1-1 Cortex-A9 Processor Mbist Interface Signals
Cortex-A9 processor. See Appendix A Signal Descriptions for descriptions of the MBIST controller interface signals. See the Cortex-A9 Processor Technical Reference Manual for more information about the MBIST interface. Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential...
Page 23: Product Revisions
- r1p0 There are no functionality changes. You must use the correct corresponding revision of MBIST controller with corresponding processor revision. For example, use an r1p0 processor with an r1p0 MBIST controller. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 25: Chapter 2 Functional Description
MBIST engine, detecting failures, and retrieving the data log. It contains the following sections: • Functional overview on page 2-2 • Functional operation on page 2-15. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 26: Functional Overview
SCU tag RAM way 3 [19] [22:0] [22:0] [54:32] [8:0] SCU tag RAM way 2 [19] [22:0] [22:0] [22:0] [8:0] SCU tag RAM way 1 [18] [22:0] [22:0] [54:32] [8:0] Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 27 5 (way 2 high) Instruction data RAM [31:0] [31:0] [10:0] array 4 (way 2 low) Instruction data RAM [63:32] [63:32] [10:0] array 3 (way 1 high) ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 28 Outer RAM on page 2-8 • Branch Target Address Cache RAM on page 2-8 • TLB RAM on page 2-9 • Global History Buffer RAMs on page 2-10. Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 29: Table 2-3 Data Data Ram Byte Write Enable Control
Data data RAMs have a byte write enable, controlled by MBISTBE[3:0] as shown in Table 2-3. Table 2-3 Data data RAM byte write enable control MBISTBE bit Description Byte 0, bits [7:0] ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 30: Table 2-4 Mbistarray Bit Usage For Tag Rams
Figure 2-3 and Figure 2-4 on page 2-7 show the data mapping on MBISTINDATA and MBISTOUTDATA buses for Instruction tag RAM. MBISTINDATA[63:0] Unused Data in [21:0] for array n Figure 2-3 Data in for Instruction tag RAM Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 31: Figure 2-4 Data Out For Instruction Tag Ram
Unused Figure 2-6 Data out for Data tag RAM and SCU tag RAM ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 32: Table 2-5 Tag Ram Control
The target array is always 32 bits wide. MBISTARRAY[1:0] selects the BTAC array. They are word-writable, controlled by MBISTWRITEEN when in BIST mode. Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 33: Figure 2-9 Data In For Btac Ram
Figure 2-11 and Figure 2-12 on page 2-10 show the data mapping on MBISTINDATA and MBISTOUTDATA buses for TLB RAM. MBISTINDATA[63:0] Data in [60:0] for array 0 used 63 62 Figure 2-11 Data in for TLB RAM ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 34: Figure 2-12 Data Out For Tlb Ram
2.1.3 MBIST controller implementation The MBIST controller block shown in Figure 2-14 on page 2-11 contains two major blocks: • MBIST controller • dispatch unit. 2-10 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 35: Table 2-6 Mbisttx Signals
MBISTTX bit Description Reset address Increment address Access sacrificial row, used during bang patterns Invert data/instruction data in Checkerboard data Write data Read data Yfast/nXfast Direction ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 2-11 Non-Confidential Restricted Access...
Page 36: Table 2-7 Mbistrx Signals
MBISTRX[5:0] This signal is an output of the dispatch unit that goes to the MBIST controller. The behavior of MBISTRX[5:0] is ARM-specific and is intended for use only with the MBIST controller. The address expire signal is set when both the row and column address counters expire.
Page 37: Table 2-8 Mbist Controller Top Level I/O
During tests, the MBISTRESULT[1] signal indicates failures. You can operate using two modes, by configuring bit [5] of the engine control section of the instruction register. If bit [5] is set, the MBISTRESULT[1] ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 2-13 Non-Confidential Restricted Access...
Page 38 At the completion of the test, the MBISTRESULT[0] signal goes HIGH. The MBISTRESULT[5:2] signal indicates that an address expire for CPU0 has occurred and enables you to measure sequential progress through the test algorithms. 2-14 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 39: Functional Operation
ATE, the PLL is in bypass mode, and the clock is not running at test frequency. MBISTRUN MBISTSHIFT MBISTDATAIN i[0] i[1] i[57] Figure 2-15 Loading the MBIST controller instruction ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 2-15 Non-Confidential Restricted Access...
Page 40: Figure 2-16 Starting The Mbist Test
Figure 2-18 on page 2-17 and Figure 2-19 on page 2-17 show the method of retrieving a data log. Note MBISTRESULT[2] is the serial data output for instructions and the data log for CPU0. 2-16 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 41: Figure 2-18 Start Of Data Log Retrieval
When the last data log bit shifts out, drive MBISTDSHIFT LOW as Figure 2-19 shows. MBISTRESULT[2] MBISTDSHIFT D[76] D[77] D[78] MBISTRESULT[5:2] MBISTRUN Figure 2-19 End of data log retrieval ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 2-17 Non-Confidential Restricted Access...
Page 42: Table 2-9 Data Log Format
The fault might be logged multiple times depending on the number of reads performed by the algorithm and the exact nature of the fault. 2-18 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential...
Page 43: Figure 2-21 End Of Bitmap Data Log Retrieval
Functional Description MBISTRESULT[1] MBISTDSHIFT MBISTRESULT[5:2] D[76] D[77] D[78] MBISTRUN Figure 2-21 End of bitmap data log retrieval Loading a new instruction resets bitmap mode. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 2-19 Non-Confidential Restricted Access...
Page 45: Chapter 3 Mbist Instruction Register
MBIST controller. It contains the following sections: • About the MBIST instruction register on page 3-2 • Field descriptions on page 3-4. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 46: About The Mbist Instruction Register
CacheSize Figure 3-2 MBIST instruction register dispatch unit The dispatch unit contains the following fields: CPU On Controls the data comparison for the CPUs under test. Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 47 Specifies 4, 8, 16, or 32 columns per block of RAM. CacheSize Specifies a cache size of 16KB, 32KB, or 64KB. Field descriptions on page 3-4 describes the MBIR fields in more detail. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 48: Field Descriptions
Tests memory failure detection capability b000110 Read Write March (x-fast) Read write march pattern, incrementing X-address first b000111 Read Write March (y-fast) Read write march pattern incrementing Y-address first Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 49 March C+ (x-fast or y-fast) This is the industry-standard March C+ algorithm: (w0) (r0, w1, r1) (r1, w0, r0) ⇓ (r0, w1, r1) ⇓ (r1, w0, r0) (r0) ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 50: Table 3-2 Go/No-Go Test Pattern
This test suite provides a comprehensive test of the arrays. The series of tests in Go/No-Go are the result of the experience in memory testing by ARM memory test engineers. Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential...
Page 51: Table 3-3 Control Field Encoding (Five Lsb Bits)
Even if the RAM under test uses the same latency for both read and write operations, you must still program both the read latency and write latency fields of the MBIR with the same value. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 52: Table 3-4 Read Latency Field Encoding
Number of cycles per write operation b000 b001 b010 b011 b100 b101 b110 b111 3.2.4 CPU On field, MBIR[39:36] The CPU On field controls data comparison for the CPUs under test. Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 53: Table 3-6 Mbir[39:36] Cpu Mapping
Determine how many address bits the RAM requires. See the Cortex-A9 Processor Configuration and Sign-off Guide for more information. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 54: Table 3-7 Maxxaddr Field Encoding
The MaxYAddr field specifies the number of Y-address counter bits to use during test. Table 3-8 shows the MaxYAddr settings. Table 3-8 MaxYAddr field encoding MaxYAddr MBIR[31:28] Number of counter bits <b0010 Unsupported b0010 b0011 b0100 b0101 3-10 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 55: Table 3-9 Arrayenables Field Encoding
BTAC RAM control array 0 and target array 0 b00000000000000000010 BTAC RAM control array 1 and target array 1 b00000000000000000100 Instruction tag RAM arrays 0 and 1 ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 3-11 Non-Confidential Restricted Access...
Page 56 MBIST operations, for example bit-line stress testing and writing a true physical checkerboard pattern to the array. 3-12 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 57: Table 3-10 Columnwidth Field Encoding
Table 3-11 shows the supported cache sizes. Table 3-11 CacheSize field encoding CacheSize MBIR[1:0] Cache size 16KB 32KB 64KB Reserved a. Mapped internally to 16KB ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 3-13 Non-Confidential Restricted Access...
Page 59: Chapter 4 Mbist Datalog Register
This chapter describes the MBIST Datalog Register. It contains the following sections: • About the MBIST Datalog Register on page 4-2 • Field descriptions on page 4-3. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 60: About The Mbist Datalog Register
The datalogs for all CPUs are dumped in parallel through MBISTRESULT[5:2] with: • MBISTRESULT[5] for CPU3 • MBISTRESULT[4] for CPU2 • MBISTRESULT[3] for CPU1 • MBISTRESULT[2] for CPU0. Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 61: Field Descriptions
64 bits that contain an XOR between failing data and correct data. All bits at1’b1 are failing. Datalog[3:0] 4 bits that contain the expected data seed. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 63 This appendix describes the MBIST controller signals. It contains the following sections: • MBIST controller interface signals on page A-2 • Miscellaneous signals on page A-4. ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 64: Table A-1 Mbist Controller Interface Signals
Instruction data RAM way 3 (blocks 6 and 7) Global History Buffer TLB RAM array 0 TLB RAM array 1 Data tag RAM arrays 0 and 1 Data tag RAM arrays 2 and 3 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 65 Data data RAM way 2 (blocks 2 and 6) Data data RAM way 3 (blocks 3 and 7) Douter RAM SCU tag RAM arrays 0 and 1 SCU tag RAM arrays 2 and 3 ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 66: Table A-3 Miscellaneous Signals
Data log shift MBISTRESETN Input MBIST reset MBISTRESULT[5:0] Output Output status bus MBISTRUN Input Run MBIST test MBISTSHIFT Input Instruction shift MBISTENABLE Input MBIST mode enable Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 67: Table B-1 Differences Between Issue A And Issue B
Table 2-1 on page 2-2 Updated bit information for the MBIST controller interfaces Table 2-2 on page 2-2 Clarified data in for Instruction tag RAM Figure 2-3 on page 2-6 ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Non-Confidential Restricted Access...
Page 68 Table 2-5 on page 2-8 Updated TLB RAM description TLB RAM on page 2-9 Updated Branch Target Address Cache RAM description Branch Target Address Cache RAM on page 2-8 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 69 Glossary This glossary describes some of the terms used in technical documents from ARM Limited. An address that comprises a tag, an index, and a word field. The tag bits identify the way Block address that contains the matching cache entry for a cache hit. The index bits identify the set being addressed.
Page 70 Cache terminology diagram The diagram illustrates the following cache terminology: • block address • cache line • cache set • cache way • index • tag. Glossary-2 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C Non-Confidential Restricted Access...
Page 71 Index Word Byte Cache way Cache set Word number Cache line Line number Cache tag RAM Cache data Read data (way number) (way that corresponds) ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. Glossary-3 Non-Confidential Restricted Access...

This manual is also suitable for:

Cortex -a9

ARM Cortex-A9 MBIST Technical Reference Manual

Preface

Chapter 1 Introduction

Chapter 2 Functional Description

Chapter 3 MBIST Instruction Register

Chapter 4 MBIST Datalog Register

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