ARM PrimeCell PL241 Technical Reference Manual

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PrimeCell

AHB SRAM/NOR

Memory Controller (PL241)

Revision: r0p1

Technical Reference Manual

ARM DDI 0389B

Table of Contents

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Summary of Contents for ARM PrimeCell PL241

Page 2: Change History
PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual Copyright © 2006 ARM Limited. All rights reserved. Release Information The following changes have been made to this book. Proprietary Notice Words and logos marked with other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.
Page 3: Table Of Contents
Contents PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual Preface Chapter 1 Introduction Chapter 2 Functional Overview Chapter 3 Programmer’s Model ARM DDI 0389B About this manual ... x Feedback ... xiv About the AHB MC ... 1-2 Supported devices ... 1-5 Functional description ...
Page 4 Contents Chapter 4 Programmer’s Model for Test Chapter 5 Device Driver Requirements Appendix A Signal Descriptions Glossary SMC integration test registers ... 4-2 Memory initialization ... 5-2 About the signals list ... A-2 Clocks and resets ... A-3 AHB signals ... A-4 SMC memory interface signals ...
Page 5 List of Tables PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual Change History ... ii Table 2-1 Static memory clocking options ... 2-12 Table 2-2 Asynchronous read opmode chip register settings ... 2-28 Table 2-3 Asynchronous read SRAM cycles register settings ... 2-28 Table 2-4 Asynchronous read in multiplexed-mode opmode chip register settings ...
Page 6 List of Tables Table 2-21 Synchronous read and asynchronous write opmode chip register settings ... 2-37 Table 3-1 Register summary ... 3-4 Table 3-2 smc_memc_status Register bit assignments ... 3-6 Table 3-3 smc_memif_cfg Register bit assignments ... 3-7 Table 3-4 smc_memc_cfg_set Register bit assignments ...
Page 7 List of Figures PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual Key to timing diagram conventions ... xii Figure 1-1 AHB MC (PL241) configuration ... 1-2 Figure 2-1 AHB MC (PL241) configuration ... 2-2 Figure 2-2 AHB MC (PL241) clock domains ... 2-3 Figure 2-3 SMC block diagram ...
Page 8 List of Figures Figure 2-20 Synchronous burst read in multiplexed-mode ... 2-34 Figure 2-21 Synchronous burst write ... 2-35 Figure 2-22 Synchronous burst write in multiplexed-mode ... 2-36 Figure 2-23 Synchronous read and asynchronous write ... 2-38 Figure 3-1 SMC register map ... 3-2 Figure 3-2 SMC configuration register map ...
Page 9: Preface
Preface This preface introduces the PrimeCell AHB SRAM/NOR Memory Controller (MC) (PL241) Technical Reference Manual. It contains the following sections: • About this manual on page x • Feedback on page xiv. ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Page 10: About This Manual
Preface About this manual This is the Technical Reference Manual (TRM) for the PrimeCell AHB SRAM/NOR Memory Controller. Product revision status The rnpn identifier indicates the revision status of the product described in this manual, where: Intended audience This manual is written for system designers, system integrators, and verification engineers who are designing a System-on-Chip (SoC) device that uses the AHB MC.
Page 11 Appendix A Signal Descriptions Glossary Conventions Conventions that this manual can use are described in: • Typographical • Timing diagrams on page xii • Signals on page xii • Numbering on page xiii. Typographical The typographical conventions are: italic bold monospace monospace monospace italic...
Page 12: Timing Diagrams
Preface Timing diagrams The figure named Key to timing diagram conventions explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams. Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time.
Page 13: Further Reading
Prefix B Prefix C Prefix H Prefix P Prefix R Prefix W Numbering The Verilog numbering convention is: <size in bits>'<base><number> Further reading This section lists publications by ARM Limited, and by third parties. ARM Limited periodically provides updates and corrections to its documentation. See http://www.arm.com Questions list.
Page 14: Feedback
Preface Feedback ARM Limited welcomes feedback on the AHB MC and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier giving: • the product name • a concise explanation of your comments. Feedback on this manual If you have any comments on this manual, send email to •...
Page 15: Chapter 1 Introduction
Chapter 1 Introduction This chapter introduces the AHB MC. It contains the following sections: • About the AHB MC on page 1-2 • Supported devices on page 1-5. ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Page 16: About The Ahb Mc
Introduction About the AHB MC The AHB MC is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral. It is developed, tested, and licensed by ARM Limited. The AHB MC takes advantage of the newly developed Static Memory Controller (SMC).
Page 17: Ahb Interface
1.1.1 AHB interface The interface converts the incoming AHB transfers to the protocol used internally by the AHB MC. The interface has the following features: • all AHB fixed length burst types are directly translated to fixed length bursts • all undefined length INCR bursts are converted to INCR4 bursts •...
Page 18: Clock Domains
Introduction 1.1.3 The SMC is a high-performance, area-optimized SRAM memory controller. The SMC is pre-configured and validated for: • the SRAM memory type • the number of SRAM memory devices • the maximum SRAM memory width. The SRAM memory interface type is defined as supporting: •...
Page 19: Supported Devices
Supported devices The SMC supports SRAM/NOR, see SMC on page 1-4. The Release Note provides a specific list of memory devices tested with each configuration. Some memory devices or series of memory devices have specific requirements: Intel W18 series NOR FLASH, for example 28f128W18td Cellular RAM 1.0, 64MB PSRAM, for example mt45w4mw16bfb_701_1us Because the memory controller maps INCR transfers into INCR4 transfers, it does not support memory mapped FIFO components.
Page 21: Chapter 2 Functional Overview
Chapter 2 Functional Overview This chapter describes the major components of the AHB MC and how they operate. It contains the following sections: • Functional description on page 2-2 • SMC on page 2-4 • Functional operation on page 2-7. •...
Page 22: Functional Description
Functional Overview Functional description Figure 2-1 shows an AHB MC (PL241) configuration. This section is divided into: • AHB interface • AHB to APB bridge • Clock domains on page 2-3 • Low-power interface on page 2-3 • SMC on page 2-4. 2.1.1 AHB interface The AHB MC fully supports the AMBA AHB 2.0 specification.
Page 23: Figure 2-2 Ahb Mc (Pl241) Clock Domains
2.1.3 Clock domains The memory controller has two clock domains: AHB clock domain Static memory clock domain Figure 2-2 shows the two clock domains. The memory controller supports many different options for clocking the different domains. See Clock domain operation on page 2-11 for more information. 2.1.4 Low-power interface The memory controller has two low-power interfaces, one for each clock domain.
Page 24: Figure 2-3 Smc Block Diagram
Functional Overview Figure 2-3 shows a block diagram of the SMC. The main blocks of the SMC are: • SMC interface on page 2-5 • APB slave interface on page 2-5 • Format on page 2-5 • Memory manager on page 2-5 •...
Page 25: Memory Manager
2.2.1 SMC interface The SMC interface processes the incoming AHB transfers and sends them to the command format block. 2.2.2 APB slave interface The SMC has 4KB of memory allocated to it. The APB slave interface accesses the SMC registers to program the memory system configuration parameters and to provide status information.
Page 26: Pad Interface
Functional Overview 2.2.6 Pad interface The pad interface module provides a registered I/O interface for data and control signals. It also contains interrupt generation logic. Figure 2-4 shows the SRAM pad interface external signals. Clock and reset signals are omitted. 2.2.7 Interrupts The SRAM memory interface support interrupts.
Page 27: Functional Operation
Functional operation This section is divided into: • AHB interface operation • AHB to APB bridge operation on page 2-10 • Clock domain operation on page 2-11 • Low-power interface operation on page 2-12 • SMC functional operation on page 2-15. 2.3.1 AHB interface operation This section describes:...
Page 28 Functional Overview Undefined length INCR bursts All undefined length INCR bursts are converted to INCR bursts of length four. Many AHB masters rely on using undefined length INCR bursts to access data. If each INCR transfer is processed as a single transfer by the internal protocol then the performance is significantly degraded.
Page 29 Functional Overview If transfers are described as non-bufferable then the bridge must wait for the write response to indicate that the transfer has been completed to memory. If numerous bufferable writes are performed, followed by a non-bufferable write, then the bridge must wait until it receives the write response associated with the final write.
Page 30: Figure 2-5 Big-Endian Implementation
Functional Overview Registered HWDATA The interconnect used within the AHB MC contains combinatorial paths for the write data. To improve the synthesis timing, HWDATA is registered and makes these paths internal to the design. Big-endian 32-bit mode The AHB MC supports the option of storing data to memory in big-endian 32-bit mode. Each bridge contains the logic to implement this data mapping depending on the big_endian input tie-off.
Page 31: Figure 2-6 Ahbc Memory Map
The other fourteen 4KB regions are read as zero. The lower 16 bits of the AHB address decode the memory controller that is being used. An external AHB decoder determines where in the system memory map, this 64KB region is located. See About the programmer’s model on page 3-2 for information on the internal memory controller configuration registers.
Page 32: Table 2-1 Static Memory Clocking Options
Functional Overview Static memory clocking options Table 2-1 lists the static memory clocking options. Options Fully synchronous hclk = smc_mclk0 Synchronous multiples hclk = n x smc_mclk0 where: n = integer value m x hclk = smc_mclk0 where: m = integer value Asynchronous Extra registers are used to avoid metastability when crossing the asynchronous clock boundary.
Page 33: Figure 2-7 Request To Enter Low-Power Mode
Functional Overview an active output <domain>_cactive Where: <domain> is ahb or smc. Figure 2-7 explains the protocol for the interface by showing a request to enter low-power mode. Figure 2-7 Request to enter low-power mode The memory controller receives a request to enter low-power mode, indicated by <domain>_csysreq being driven LOW by the system clock controller, as shown at T1.
Page 34: Figure 2-9 Accepting Requests
Functional Overview The AHB domain accepts or denies requests based on whether it is busy performing any transfers. Figure 2-9 shows that static memory controllers always accept requests after they have performed the required operations to prepare the external memory for the clock to be switched off.
Page 35: Smc Functional Operation
SMC functional operation This section describes: • Operating states • Clocking and resets on page 2-16 • Miscellaneous signals on page 2-18 • APB slave interface operation on page 2-19 • Format block on page 2-19 • Memory manager operation on page 2-22 •...
Page 36: Clocking And Resets
Functional Overview The state transitions are: Ready to Reset Reset to Ready Ready to Low-power Low-power to Ready Low-power to Reset 2.4.2 Clocking and resets This section describes: • Clocking • Resets on page 2-17. Clocking All configurations of the SMC support at least two clock domains, and have the following clock inputs: •...
Page 37 These clocks can be grouped into two clock domains: AHB domain Memory clock domain You can tie off the smc_async and smc_msync pins so that the smc_aclk and smc_mclk0 clock domains can operate synchronously or asynchronously with respect to each other. Synchronous clocking Asynchronous clocking Output clocks...
Page 38: Miscellaneous Signals
Functional Overview You can change both reset signals asynchronously to their respective clock domain. Internally to the SMC the deassertion of the hresetn signal is synchronized to smc_aclk. The deassertion of smc_mreset0n is synchronized internally to smc_mclk0 and smc_mclk0n. 2.4.3 Miscellaneous signals You can use the following signals as general-purpose control signals for logic external to the SMC:...
Page 39 smc_msync0 smc_rst_bypass smc_use_ebi 2.4.4 APB slave interface operation To enable a clean registered interface to the external infrastructure, the APB interface always adds a wait state for all reads and writes by driving pready LOW during the first cycle of the access phase. In two instances, a delay of more than one wait state can be generated: •...
Page 40 Functional Overview The SMC ensures the ordering of read transfers from a single port is maintained RAR, and additionally that the ordering of write transfers from a single master is maintained WAW. SRAM memory accesses This section describes: • Standard SRAM access •...
Page 41 Functional Overview memory bursts, terminating a memory transfer at the burst boundary. Also ensure the page size is an integer multiple of the burst length, to avoid a memory burst crossing a page boundary. When the burst_align bit is not set, the SMC ignores the memory burst boundary when mapping commands onto memory commands.
Page 42: Low-Power Operation
Functional Overview 2.4.6 Memory manager operation The memory manager module is responsible for controlling the state of the SMC and the updating of chip configuration registers. This subsection describes: • Low-power operation • Chip configuration registers • Direct commands on page 2-24. Low-power operation The SMC accepts requests to enter the Low-power state through either the SMC low-power interface or the APB register interface.
Page 43: Figure 2-11 Chip Configuration Registers
The APB registers smc_set_cycles and smc_set_opmode act as holding registers, the configuration registers within the manager are only updated if either: • the smc_direct_cmd Register indicates only a register update is taking place • the smc_direct_cmd Register indicates either a modereg operation or an memory access has taken place, and is complete.
Page 44: Direct Commands
Functional Overview Direct commands The SMC enables code to be executed from the memory while simultaneously, from the software perspective, moving the same chip to a different operating mode. This is achieved by synchronizing the update of the chip configuration registers from the holding registers with the dispatch of the memory configuration register write.
Page 47 2.4.7 Interrupts operation The next read to any chip select on the appropriate memory interface clears the interrupt. The interrupt outputs are generated through a combinational path from the relevant input pin. This enables you to place the SMC in Low-power state, and to stop the clocks while waiting for an interrupt.
Page 48: Table 2-2 Asynchronous Read Opmode Chip Register Settings
Functional Overview Read data output by the memory device is also registered on the rising edge of smc_mclk0n, equivalent to the falling edge of smc_mclk0, for asynchronous reads. For synchronous reads, read data is registered using the fed back clock, smc_fbclk_in. For synchronous and asynchronous accesses, the data is then pushed onto the read data FIFO to be returned by the SMC interface.
Page 49: Table 2-4 Asynchronous Read In Multiplexed-Mode Opmode Chip Register Settings
Asynchronous read in multiplexed-mode Table 2-4 and Table 2-5 list the smc_opmode0_<0-3> and SRAM Register settings. Table 2-4 Asynchronous read in multiplexed-mode opmode chip register settings Table 2-5 Asynchronous read in multiplexed-mode SRAM cycles register settings Figure 2-15 shows a single asynchronous read transfer in multiplexed-SRAM mode, with t ARM DDI 0389B Field...
Page 50: Table 2-6 Asynchronous Write Opmode Chip Register Settings
Functional Overview In multiplexed-mode, both address and data are output by the SMC on the smc_data_out_0[31:0] output bus. Read data is accepted on the smc_data_in_0[31:0] bus. Asynchronous write Table 2-6 and Table 2-7 list the smc_opmode0_<0-3> and SRAM Register settings. Figure 2-16 shows an asynchronous write with a write cycle time t a smc_we_n_0 assertion duration, t The timing parameter t...
Page 51: Table 2-8 Asynchronous Write In Multiplexed-Mode Opmode Chip Register Settings
Asynchronous write in multiplexed-mode Table 2-8 and Table 2-9 list the smc_opmode0_<0-3> and SRAM Register settings. Table 2-8 Asynchronous write in multiplexed-mode opmode chip register settings Table 2-9 Asynchronous write in multiplexed-mode SRAM cycles register settings Figure 2-17 shows an asynchronous write in multiplexed-mode. t is four cycles, and is extended by two cycles for the address phase of the transaction.
Page 52: Table 2-12 Synchronous Burst Read Opmode Chip Register Settings
Functional Overview Figure 2-18 shows a page read access, with an initial access time, t an output enable assertion delay, t cycle. Page mode is enabled in the SMC by setting the opmode Register for the relevant chip to asynchronous reads and the burst length to the page size. Multiplexed-mode page accesses are not supported.
Page 53: Figure 2-19 Synchronous Burst Read
Figure 2-19 shows a burst read with the smc_wait_0 output of the memory used to delay the transfer. • Synchronous memories have a configuration register enabling smc_wait_0 to be asserted either on the same clock cycle as the delayed data or a cycle earlier. The SMC only supports smc_wait_0 being asserted one cycle early, enabling smc_wait_0 to be initially sampled with the fed back clock and then with smc_mclk0 before being used by the FSM.
Page 54: Figure 2-20 Synchronous Burst Read In Multiplexed-Mode
Functional Overview Synchronous burst read in multiplexed-mode Table 2-14 and Table 2-15 list the smc_opmode0_<0-3> and SRAM Register settings. Table 2-14 Synchronous burst read in multiplexed-mode opmode chip register Field Value Figure 2-20 shows the same synchronous read burst transfer as Figure 2-19 on page 2-33, but in multiplexed-mode.
Page 55: Table 2-16 Synchronous Burst Write Opmode Chip Register Settings
Synchronous burst write Table 2-16 and Table 2-17 list the smc_opmode0_<0-3> and SRAM Register settings. Field Value Figure 2-21 shows a synchronous burst write transfer that is delayed by the smc_wait_0 signal. You must configure the memory to assert smc_wait_0 one cycle early and with an active LOW priority.
Page 56: Figure 2-22 Synchronous Burst Write In Multiplexed-Mode
Functional Overview Synchronous burst write in multiplexed-mode Table 2-18 and Table 2-19 list the smc_opmode0_<0-3> and SRAM Register settings. Table 2-18 Synchronous burst write in multiplexed-mode opmode chip register Field Value Table 2-19 Synchronous burst write in multiplexed-mode SRAM cycles register Figure 2-22 shows the same synchronous burst write as Figure 2-21 on page 2-35, but in multiplexed-mode.
Page 57 Synchronous read and asynchronous write Table 2-20 and Table 2-21 list the smc_opmode0_<0-3> and SRAM Register settings. Table 2-20 Synchronous read and asynchronous write opmode chip register Field Value Table 2-21 Synchronous read and asynchronous write opmode chip register Figure 2-23 on page 2-38 shows the turnaround time t synchronous read and asynchronous write.
Page 58: Figure 2-23 Synchronous Read And Asynchronous Write
Functional Overview Programming t For t • when using memory devices that are not wait-enabled, you must program t be the number of clock cycles required before valid data is available following the assertion of cs_n • when using memory devices that are wait-enabled, you must program t the number of clock cycles required before wait is active and stable, following the assertion of cs_n.
Page 59 For t • when using memory devices that are not wait-enabled, you must program t be the number of clock cycles required before the first data is written, following the assertion of cs_n • when using memory devices that are wait-enabled, you must program t the number of clock cycles required before wait is active and stable, following the assertion of cs_n.
Page 61: Programmer's Model
Chapter 3 Programmer’s Model This chapter describes the registers of the SMC and provides information for programming the device. It contains the following sections: • About the programmer’s model on page 3-2 • Register summary on page 3-3 • Register descriptions on page 3-6. ARM DDI 0389B Copyright ©...
Page 62: About The Programmer's Model
Programmer’s Model About the programmer’s model The SMC has 4KB of memory allocated to it from a base address of maximum address of split into the following regions: SMC configuration registers SMC chip select configuration registers SMC user configuration registers SMC integration test registers SMC PrimeCell Id registers .
Page 63: Register Summary
Register summary Figure 3-2 shows the SMC configuration register map. Figure 3-3 shows the SMC chip< ARM DDI 0389B > configuration register map: Figure 3-3 SMC chip configuration register map Copyright © 2006 ARM Limited. All rights reserved. Programmer’s Model Figure 3-2 SMC configuration register map...
Page 64: Table 3-1 Register Summary
Programmer’s Model Figure 3-3 on page 3-3 shows the maximum number of supported chips. If you intend to use fewer, then the highest chip configuration blocks of the correct type are read back as zero. Figure 3-4 shows the SMC user configuration memory register map. Figure 3-5 shows the SMC peripheral and PrimeCell configuration register map.
Page 65 Name Base offset smc_set_cycles 0x1014 smc_set_opmode 0x1018 smc_refresh_period_0 0x1020 smc_sram_cycles0_<0-3> 0x1000 configuration base address smc_opmode0_<0-3> 0x1004 + configuration base address smc_user_status 0x1200 smc_user_config 0x1204 smc_int_cfg 0x1E00 smc_int_inputs 0x1E04 smc_int_outputs 0x1E08 smc_periph_id_<0-3> 0x1FE0-0x1FEC smc_pcell_id_<0-3> 0x1FF0-0x1FFC ARM DDI 0389B Type Reset value 0x00000000 + chip 0x0002B3CC...
Page 66: Register Descriptions
Programmer’s Model Register descriptions This section describes the SMC registers. 3.3.1 SMC Memory Controller Status Register at 0x1000 The read-only smc_memc_status Register provides information on the configuration of the SMC and also the current state of the SMC. This register cannot be read in the Reset state.
Page 67: Table 3-3 Smc_Memif_Cfg Register Bit Assignments
3.3.2 SMC Memory Interface Configuration Register at 0x1004 The read-only smc_memif_cfg Register provides information on the configuration of the memory interface. This register cannot be read in the Reset state. Figure 3-7 shows the register bit assignments. Table 3-3 lists the register bit assignments. Bits Name Function...
Page 68: Figure 3-8 Smc_Memc_Cfg_Set Register Bit Assignments
Programmer’s Model Bits Name Function [3:2] memory_chips0 Returns the number of different chip selects that the memory interface 0 supports: b00 = 1 chip b01 = 2 chips b10 = 3 chips b11 = 4 chips. [1:0] memory_type0 Returns the memory interface 0 type: b00 = reserved b01 = SRAM b10 = NAND...
Page 69: Table 3-4 Smc_Memc_Cfg_Set Register Bit Assignments
Table 3-4 lists the register bit assignments. Bits Name [31:3] low_power_req int_enable0 3.3.4 SMC Clear Configuration Register at 0x100C The write-only smc_memc_cfg_clr Register enables the memory controller to be moved out of the Low-power state, and the interrupts disabled. This register cannot be written to in the Reset state.
Page 70: Table 3-6 Smc_Direct_Cmd Register Bit Assignments
Programmer’s Model 3.3.5 SMC Direct Command Register at 0x1010 The write-only smc_direct_cmd Register passes commands to the external memory, and controls the updating of the chip configuration registers with values held in the set_opmode and set_cycles registers. This register cannot be written to in either the Reset or Low-power state. Figure 3-10 shows the register bit assignments.
Page 71: Table 3-7 Smc_Set_Cycles Register Bit Assignments
3.3.6 SMC Set Cycles Register at 0x1014 This is the holding register for the smc_set_cycles0_<n>. The write-only smc_set_cycles Register enables the time interval to be set for holding registers before data can be written to the memory manager specific registers. This register cannot be written to in either the Reset or Low-power state.
Page 72: Figure 3-12 Smc_Set_Opmode Register Bit Assignments
Programmer’s Model 3.3.7 SMC Set Opmode Register at 0x1018 This register is the holding register for the smc_opmode0_<n> working registers. The write-only smc_set_opmode Register cannot be written to in either the Reset or Low-power state. Figure 3-12 shows the register bit assignments. Table 3-8 on page 3-13 describes register holding, see Memory manager operation on page 2-22 for more information.
Page 73: Table 3-8 Smc_Set_Opmode Register Bit Assignments
Table 3-8 lists the register bit assignments. Bits Name Function [31:16] Reserved, undefined, write as zero. [15:13] set_burst_align Holding register for value to be written to the specific SRAM chip opmode Register burst_align field. These bits determine whether memory bursts are split on memory burst boundaries: 000 = bursts can cross any address boundary 001 = burst split on memory burst boundary, that is, 32 beats for continuous 010 = burst split on 64 beat boundary...
Page 74 Programmer’s Model Bits Name Function [9:7] set_wr_bl Holding register for value to be written to the specific SRAM chip smc_opmode Register bls field. Encodes the memory burst length: b000 = 1 beat b001 = 4 beats b010 = 8 beats b011 = 16 beats b100 = 32 beats b101 = continuous...
Page 75: Table 3-9 Smc_Refresh_Period_0 Register Bit Assignments
3.3.8 SMC Refresh Period 0 Register at 0x1020 The read/write smc_refresh_period_0 Register enables the AHB MC to perform refresh cycles for PSRAM devices that you connect to memory interface 0. You cannot access this register in either the Reset or low-power states. Figure 3-13 shows the register bit assignments.
Page 76: Table 3-10 Smc_Sram_Cycles Register Bit Assignments
Programmer’s Model Table 3-10 lists the register bit assignments. 3.3.10 SMC Opmode Registers <0-3> at 0x1104, 0x1124, 0x1144, 0x1164 There is an instance of the smc_opmode Register for each chip supported. This register is read-only and cannot be read in the Reset state. The reset values of these registers are configuration-dependent.
Page 77: Table 3-11 Smc_Opmode Register Bit Assignments
Table 3-11 lists the register bit assignments. Bits Name Function [31:24] address_match Returns the value of this tie-off. This is the comparison value for address bits [31:24] to determine the chip that is selected. [23:16] address_mask Returns the value of this tie-off. This is the mask for address bits[31:24] to determine the chip that must be selected.
Page 78: Table 3-12 Smc_User_Status Register Bit Assignments
Programmer’s Model Bits Name Function wr_sync When set, the memory operates in write sync mode. [5:3] rd_bl Determines the memory burst lengths for reads: b000 = 1 beat b001 = 4 beats b010 = 8 beats b011 = 16 beats b100 = 32 beats b101 = continuous b110-b111 = reserved.
Page 79: Table 3-13 Smc_User_Config Register Bit Assignments
3.3.12 SMC User Configuration Register at 0x1204 The smc_user_config Register is a general purpose write-only register. This register sets the value of the smc_user_config[7:0] primary outputs. The smc_user_config Register can be written in all states. Figure 3-17 shows the register bit assignments. Table 3-13 lists the register bit assignments.
Page 80: Table 3-15 Smc_Periph_Id_0 Register Bit Assignments
Programmer’s Model Figure 3-18 shows the correspondence between bits of the smc_ periph_id registers and the conceptual 32-bit Peripheral ID Register. The following section describe the smc_periph_id Registers • SMC Peripheral Identification Register 0 • SMC Peripheral Identification Register 1 on page 3-21 •...
Page 81: Table 3-16 Smc_Periph_Id_1 Register Bit Assignments
SMC Peripheral Identification Register 1 The smc_periph_id_1 Register is hard-coded and the fields within the register indicate the value. Table 3-16 lists the register bit assignments. SMC Peripheral Identification Register 2 The smc_periph_id_2 Register is hard-coded and the fields within the register indicate the value.
Page 82: Table 3-19 Smc_Pcell_Id Register Bit Assignments
Programmer’s Model 3.3.14 SMC PrimeCell Identification Registers <0-3> at 0x1FF0-0x1FFC The smc_pcell_id Registers are four 8-bit wide registers, that span address locations 0xFF0-0FFC 32-bit PrimeCell ID value. You can use the register for automatic BIOS configuration. The smc_pcell_id Register is set to wait state.
Page 83: Table 3-20 Smc_Pcell_Id_0 Register Bit Assignments
The following sections describe the smc_pcell_id Registers: • SMC PrimeCell Identification Register 0 • SMC PrimeCell Identification Register 1 • SMC PrimeCell Identification Register 2 on page 3-24 • SMC PrimeCell Identification Register 3 on page 3-24. These registers cannot be read in the Reset state. SMC PrimeCell Identification Register 0 The smc_pcell_id_0 Register is hard-coded and the fields within the register indicate the value.
Page 84: Table 3-22 Smc_Pcell_Id_2 Register Bit Assignments
Programmer’s Model SMC PrimeCell Identification Register 2 The smc_pcell_id_2 Register is hard-coded and the fields within the register indicate the value. Table 3-22 lists the register bit assignments. SMC PrimeCell Identification Register 3 The smc_pcell_id_3 Register is hard-coded and the fields within the register indicate the value.
Page 85: Chapter 4 Programmer's Model For Test
Chapter 4 Programmer’s Model for Test This chapter describes the additional logic for functional verification and production testing. It contains the following section: • SMC integration test registers on page 4-2. ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Page 86: Smc Integration Test Registers
Programmer’s Model for Test SMC integration test registers Test registers are provided for integration testing. Figure 4-1 shows the SMC integration test register map. Table 4-1 lists the SMC integration test registers. Name smc_int_cfg smc_int_inputs smc_int_outputs 4.1.1 SMC Integration Configuration Register at 0x1E00 The read/write smc_int_cfg Register selects the integration test registers.
Page 87: Table 4-2 Smc_Int_Cfg Register Bit Assignments
Table 4-2 lists the register bit assignments. Bits Name Function [31:1] Undefined Read undefined. Write as zero. int_test_en When set, outputs are driven from the integration test registers and tied-off, and inputs can change for integration testing. 4.1.2 Integration Inputs Register at 0x1E04 The read-only smc_int_inputs Register enables an external master to access the inputs of the SMC using the APB interface.
Page 88: Table 4-4 Smc_Int_Outputs Register Bit Assignments
Programmer’s Model for Test 4.1.3 Integration Outputs Register at 0x1E08 The write-only smc_int_outputs Register enables an external master to access the outputs of the SMC using the APB interface. This register cannot be read in the Reset state. Figure 4-4 shows the register bit assignments. Table 4-4 lists the register bit assignments.
Page 89: Chapter 5 Device Driver Requirements
Chapter 5 Device Driver Requirements This chapter contains various flow diagrams to aid in the development of a software driver for the SMC. It contains the following section: • Memory initialization on page 5-2. ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Page 90: Memory Initialization
Device Driver Requirements Memory initialization Figure 5-1 on page 5-3 and Figure 5-3 on page 5-5 shows the sequence of events that a device driver must carry out to initialize the memory controller and a memory device to ensure the configuration of both is synchronized. Typically, PSRAM devices can have the mode register programmed using the address bus only.
Page 91: Figure 5-1 Smc And Memory Initialization Sheet 1 Of 3
Device Driver Requirements Figure 5-1 SMC and memory initialization sheet 1 of 3 ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Page 92: Figure 5-2 Smc And Memory Initialization Sheet 2 Of 3
Device Driver Requirements Figure 5-2 SMC and memory initialization sheet 2 of 3 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B...
Page 93: Figure 5-3 Smc And Memory Initialization Sheet 3 Of 3
Device Driver Requirements Figure 5-3 SMC and memory initialization sheet 3 of 3 Where: x = denotes the appropriate chip select. ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Page 95: Appendix A Signal Descriptions
Appendix A Signal Descriptions This appendix lists and describes the processor signals. It contains the following sections: • About the signals list on page A-2 • Clocks and resets on page A-3 • AHB signals on page A-4 • SMC memory interface signals on page A-5 •...
Page 96: About The Signals List
Signal Descriptions About the signals list This appendix lists the PL241 signals. Figure A-1 shows how the signals are grouped. where: AHBC = AHB Configuration signals Figure A-1 AHB MC PL241 grouping of signals Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B...
Page 97: Clocks And Resets
Clocks and resets Table A-1 lists the clock and reset signals. ARM DDI 0389B Source/ Name Type destination hclk Input Clock source hresetn Input Reset source smc_aclk Input Clock source smc_mclk0 Input Clock source smc_mclk0n Input Clock source smc_mreset0n Input Reset source Copyright ©...
Page 98: Table A-2 Ahb Signals
Signal Descriptions AHB signals Table A-2 lists the AHB signals. where: <x> = 0 or C, where Name Type hsel<x> Input haddr<x>[31:0] Input htrans<x>[1:0] Input hwrite<x> Input hsize<x>[2:0] Input hburst<x>[2:0] Input hprot<x>[3:0] Input hwdata<x>[31:0] Input hmastlock<x> Input hready<x> Input hrdata<x>[31:0] Output hreadyout<x>...
Page 99: Smc Memory Interface Signals
SMC memory interface signals Table A-3 lists the SMC memory interface signals. ARM DDI 0389B Name Type smc_fbclk_in_0 Input smc_data_in_0[31:0] Input smc_wait_0 Input smc_int_0 Input smc_clk_out_0[3:0] Output smc_add_0[31:0] Output smc_cs_n_0[3:0] Output smc_we_n_0 Output smc_oe_n_0 Output smc_adv_n_0 Output smc_baa_n_0 Output smc_cre_0 Output smc_bls_n_0[3:0] Output...
Page 100: Smc Miscellaneous Signals
Signal Descriptions SMC miscellaneous signals Table A-4 lists the SMC miscellaneous signals. Name Type smc_async0 Input smc_msync0 Input smc_a_gt_m0_sync Input smc_address_mask0_0[7:0] Input smc_address_match0_0[7:0] Input smc_address_mask0_1[7:0] Input smc_address_match0_1[7:0] Input smc_address_mask0_2[7:0] Input smc_address_match0_2[7:0] Input smc_address_mask0_3[7:0] Input smc_address_match0_3[7:0] Input smc_remap_0 Input smc_mux_mode_0 Input smc_sram_mw_0[1:0] Input smc_user_status[7:0]...
Page 101: Table A-5 Low-Power Interface Signals
Low-power interface Table A-5 lists the low-power interface signals. Name ahb_csysreq smc_csysreq ahb_csysack ahb_cactive smc_csysack smc_cactive ARM DDI 0389B Source/ Type destination Input System controller Input System controller Output System controller Output System controller Output System controller Output System controller Copyright ©...
Page 102: Table A-6 Configuration Signal
Signal Descriptions Configuration signal Table A-6 lists the configuration signal. Source/ Name Type destination big_endian Input Tie-off Copyright © 2006 ARM Limited. All rights reserved. Table A-6 Configuration signal Description Big-endian mode configuration tie-off ARM DDI 0389B...
Page 103: A.8 Scan Chains
Scan chains Table A-7 lists the scan chain signals. Name ahb_rst_bypass smc_rst_bypass smc_dft_en_clk_out si_hclk smc_si_aclk smc_si_mclk0 smc_si_mclk0n smc_si_fbclk_in_0 smc_si_int_0 so_hclk smc_so_aclk smc_so_mclk0 smc_so_mclk0n smc_so_fbclk_in_0 smc_so_int_0 ARM DDI 0389B Source/ Type destination Input Scan chains Input Scan chains Input Scan chains Input Scan chains Input...
Page 105 Glossary This glossary describes some of the terms used in technical documents from ARM Limited. Advanced High-performance Bus (AHB) A bus protocol with a fixed pipeline between address/control and data phases. It only supports a subset of the functionality provided by the AMBA AXI protocol. The full AMBA AHB protocol specification includes a number of features that are not commonly required for master and slave IP developments and ARM Limited recommends only a subset of the protocol is usually used.
Page 106 Glossary Advanced Peripheral Bus (APB) A simpler bus protocol than AHB. It is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Connection to the main system bus is through a system-to-peripheral bus bridge that helps to reduce system power consumption.
Page 107 Boundary scan chain A boundary scan chain is made up of serially-connected devices that implement boundary scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain connected between TDI and TDO, through which test data is shifted.
Page 108 Glossary See Should Be One. See Should Be Zero. See Should Be Zero or Preserved. SBZP A scan chain is made up of serially-connected devices that implement boundary scan Scan chain technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain connected between TDI and TDO, through which test data is shifted.
Page 109 Changing the address of physical memory or devices after the application has started Remapping executing. This is typically done to permit RAM to replace ROM when the initialization has been completed. A field in a control register or instruction format is reserved if the field is to be defined Reserved by the implementation, or produces Unpredictable results if the contents of the field are not zero.

ARM PrimeCell PL241 Technical Reference Manual

Preface

Chapter 1 Introduction

Chapter 2 Functional Overview

Chapter 3 Programmer's Model

Chapter 4 Programmer's Model for Test

Chapter 5 Device Driver Requirements

Appendix A Signal Descriptions

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