ARM ARM11 Technical Reference Manual

Memory built-in self test controller

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ARM11 Memory Built-In Self Test

Controller

Technical Reference Manual

ARM DDI 0289B

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Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 3: Table Of Contents
Timing ......................2-2 Bitmap mode ....................2-6 Chapter 3 ARM11 MBIST Controller Instruction Register Instruction Register ..................3-2 Field descriptions ..................3-3 Appendix A Signal Descriptions Signal descriptions ..................A-2 ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 4 Instruction Register enables field ............... B-2 Choosing the RAM size ................B-3 Connection ....................B-12 Appendix C Integration with the ETB11 Instruction Register enables field ............... C-2 Trace RAM ....................C-3 Connection ....................C-5 Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...
Page 5 ARM11 Memory Built-In Self Test Controller Technical Reference Manual Change history ......................ii Table 1-1 ARM11 MBIST Controller interface signals ............... 1-4 Table 2-1 Format of the data log ....................2-5 Table 3-1 Register settings and resulting address sizes ............3-5 Table 3-2 Register settings and resulting address sizes ............
Page 6 List of Tables Table C-1 Enable bit RAM selection ..................C-2 Table C-2 ETB_ADDR_WIDTH and ETB11 Trace RAM locations ........... C-3 Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...
Page 7 Traditional method of interfacing MBIST ..............1-3 Figure 1-2 ARM11 processor MBIST interface ................1-4 Figure 2-1 Loading the ARM memory BIST instruction .............. 2-2 Figure 2-2 Starting the memory BIST test .................. 2-3 Figure 2-3 Detecting a failure during memory BIST ..............2-3 Figure 2-4 Start of data log retrieval ...................
Page 9: Preface
Preface This preface introduces the ARM11 Memory Built-In Self Test Controller Technical Reference Manual. It contains the following sections: • About this book on page x • Feedback on page xiii. ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 10: About This Book
Preface About this book This book provides a description of the ARM11 Memory Built-In Self Test (MBIST) Controller. Intended audience This book is written for hardware engineers who are familiar with ARM technology and want to use the ARM11 MBIST Controller to test embedded memory on ARM11-based devices.
Page 11: Key To Timing Diagram Conventions
Preface bold Highlights interface elements, such as menu names. Denotes ARM processor signal names. Also used for terms in descriptive lists, where appropriate. Denotes text that can be entered at the keyboard, such as monospace commands, file and program names, and source code.
Page 12 Prefix b Indicates binary. Further reading This section lists publications from both ARM Limited and third parties that provide additional information on developing code for the ARM family of processors. ARM periodically provides updates and corrections to its documentation. See for current errata sheets, addenda, and the ARM Frequently Asked http://www.arm.com...
Page 13: Feedback
Preface Feedback ARM Limited welcomes feedback on both the ARM11 MBIST Controller, and its documentation. Feedback on the ARM11 MBIST Controller If you have any comments or suggestions about this product, contact your supplier giving: • the product name •...
Page 15: Chapter 1 Introduction
Chapter 1 Introduction This chapter describes the ARM11 MBIST Controller. It contains the following sections: • Overview on page 1-2 • MBIST ports on page 1-3. ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 16: Overview
Many industry-standard algorithms exist. An MBIST Controller is used to generate the correct sequence of reads and writes. The ARM11 MBIST Controller can be used with some ARM products to perform embedded memory testing. ARM11 MBIST Controllers are currently available for the following products: •...
Page 17: Mbist Ports
The method shown in Figure 1-1 has the advantage of having the two cycle register-to-register path that accesses the RAM blocks using the same path in memory BIST mode as in functional mode. ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 18: Figure 1-2 Arm11 Processor Mbist Interface
MBISTWE MTESTON Figure 1-2 ARM11 processor MBIST interface The ARM11 MBIST Controller accesses the memory in this way through the MBIST interface. This contains the ports listed in Table 1-1. Table 1-1 ARM11 MBIST Controller interface signals Name Type...
Page 19 Introduction Table 1-1 ARM11 MBIST Controller interface signals (continued) Name Type Description MBISTCE Input Selects RAM blocks. One hot-chip enable for each of the RAM blocks. This signal can be a bus if required. MBISTWE Input Global write enabling signal to all of the RAM blocks.
Page 21: Chapter 2 Functional Description
Chapter 2 Functional Description This chapter provides timing and data log retrieval information for the ARM11 MBIST Controller. It contains the following sections: • Timing on page 2-2 • Bitmap mode on page 2-6. ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 22: Timing
Chapter 3 ARM11 MBIST Controller Instruction Register. It is loaded serially at the start of each test. ARM Limited recommends that you run your MBIST tests at the full frequency of the design. The timing diagrams in this section show the clock running at two different speeds: •...
Page 23: Figure 2-2 Starting The Memory Bist Test
You must normally run this using the PLL as the source of the clock to ensure the memories are tested at-speed. 2.1.4 Fail detection Figure 2-3 shows how fails can be detected by the ATE using the ARM11 MBIST Controller. REFCLK Assumes sticky fail is enabled...
Page 24: Figure 2-4 Start Of Data Log Retrieval
2.1.5 Data log retrieval During a test, the first failure to be detected is automatically logged by the ARM11 MBIST Controller. If required, you can retrieve this at the end of the test to generate failure statistics. The method of retrieving a data log is shown in Figure 2-4 and Figure 2-5.
Page 26: Bitmap Mode
When Bitmap mode is not used, the first detected failure is recorded in the data log so that it can be retrieved at the end of the test. Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...
Page 27: Chapter 3 Arm11 Mbist Controller Instruction Register
Chapter 3 ARM11 MBIST Controller Instruction Register This chapter describes the ARM11 MBIST Controller Instruction Register and associated bit assignments. It contains the following sections: • Instruction Register on page 3-2 • Field descriptions on page 3-3. ARM DDI 0289B...
Page 28: Instruction Register
Figure 3-1 shows the MBIR bit assignments. 34 33 28 27 24 23 20 19 16 15 Pattern Control Data seed Enables x-locations y -locations Figure 3-1 Memory BIST Instruction Register bit assignments Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...
Page 29: Field Descriptions
The enables field selects which RAM is tested. See Appendix B Integration with the ARM1136 Processor and Appendix C Integration with the ETB11 for specific information about the use of the field with your ARM11 MBIST Controller. 3.2.2 Data seed You specify the data seed used during the test algorithm at instruction load.
Page 30: Figure 3-2 Example Ram Topology
The remaining bits of the address select a row and are called the y-Address. The address output from each of the ARM11 MBIST Controllers is formed by concatenating the y-Address with the x-Address. This is done depending on the value of x-Locations as shown in Figure 3-3.
Page 31: Table
The y-Locations specify the number of column locations to use during test. Table 3-2 describes the register settings and resulting address sizes. Table 3-2 Register settings and resulting address sizes y-Locations Number of locations b0000 b0001 b0010 ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 32: Behavior Of The Engine Control Field
Test runs to completion, sticky fail present after first fail b00001 Stop on fail Indicates early end of test b00011 Bitmap mode Places controller into interactive mode for each failure, see Bitmap mode on page 2-6 Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...
Page 33: Table 3-4 Supported Patterns
ARM11 MBIST Controller Instruction Register 3.2.5 Pattern Industry standard patterns and an ARM created bit-line stress pattern are provided for use in MBIST. You can group algorithms together to create a specific memory test methodology for a manufacturer. Table 3-4 describes the supported patterns and Pattern specification on page 3-8 describes their use.
Page 34 This test is always performed x-fast. It executes consecutive multiple writes and reads on a bit-line pair. This pattern does detect stuck-at faults, but its primary intent is to address the analog characteristics of the memory. Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...
Page 35: Table 3-5 Go/No-Go Algorithm
This test suite provides a comprehensive test of the arrays. The series of tests in Go/No-Go are the result of past experiences of memory testing by internal ARM memory test engineers. The Data seed supplied in the instruction is ignored during this test and the data used instead is as shown in Table 3-5.
Page 37: Signal Descriptions
Appendix A Signal Descriptions This appendix describes the ARM Memory BIST signals. It contains the following sections: • Signal descriptions on page A-2 ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 38 Signal Descriptions Signal descriptions You can use the ARM Memory BIST controllers with the following macrocells: • ARM1136 • ETB11. The Memory BIST Controllers use the Memory BIST Interface implemented on these two macrocells. For more information, see: • ARM1136 Implementation Guide •...
Page 39 ARM1136 processor. It contains the following sections: • Instruction Register enables field on page B-2 • Choosing the RAM size on page B-3 • Connection on page B-12. ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 40: Instruction Register Enables Field
Table B-1 Enable bit RAM selection Enable bit RAM group name BTAC ITCM Data Cache Valid TCM Valid I Cache Tag I Cache Data Dirty DTCM Data D Cache Tag [10] D Cache Data Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...
Page 41: Choosing The Ram Size
B.2.2 BTAC RAM The BTAC RAMs are tested as a single 61-bit wide RAM with 128 locations. This size is fixed, regardless of the cache and TCM sizes. ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 42: Table B-3 Choosing Values For X- And Y-Locations, Btac Ram
512 and 2 respectively. Note If your implementation does not have an Instruction TCM, you must not run an instruction to test this RAM. Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...
Page 43: Table B-5 Cache Valid Size And Locations
B.2.5 TCM valid RAMs The TCM valid RAMs are each eight bits wide and are tested simultaneously. Logic in the ARM11 MBIST Controller ensures that data read from locations that are not implemented does not cause failures. ARM DDI 0289B...
Page 44: Table B-6 Tcm Size And Locations
RAM because of the way the RAMs are concatenated during BIST. The number of locations that must be specified in the BIST instruction depends on the size of the instruction cache. Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...
Page 45: Table B-7 Instruction Cache Size And Tag Ram Locations
Table B-8. Table B-8 Instruction cache size and data RAM locations Instruction cache Instruction data RAM cache size locations 1024 16KB 2048 32KB 4096 64KB 8192 ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 47: Table B-10 Dtcm Size And Dtcm Ram Locations
Tag RAM because of the way the RAMs are concatenated during BIST. The number of locations that must be specified in the BIST instruction depends on the size of the data cache. ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 48: Table B-11 Data Cache Size And Data Cache Tag Ram Locations
Table B-12. Table B-12 Data cache size and data cache tag RAM locations Data cache tag Data cache size RAM locations 1024 16KB 2048 32KB 4096 64KB 8192 B-10 Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...
Page 49 You must choose values for the number of x and y-Locations so that their product is equal to the number of locations given in the Table B-12 on page B-10 for your specific data cache size. ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved. B-11...
Page 50: Connection
Integration with the ARM1136 Processor Connection Connection of the ARM11 MBIST Controller to the ARM1136 processor is described in the ARM1136 Implementation Guide. B-12 Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...
Page 51: Appendix C Integration With The Etb11
Appendix C Integration with the ETB11 This appendix describes the relationship between the ETB11 address width and the number of ETB11 Trace RAM locations that you can test with the ARM11 MBIST Controller. It contains the following sections: • Instruction Register enables field on page C-2 •...
Page 52 RAMs can be selected at a time. Selecting multiple groups produces Undefined behavior. Table C-1 Enable bit RAM selection Enable bit RAM group name BIST Controller used [11] ETB Trace RAM ETB11 Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...
Page 53: Trace Ram
256K 512K Note You cannot use ARM MBIST to test your Trace RAM if it has more than 8M locations. This is 32MB if a 32-bit wide RAM is used. ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 55: Connection
Integration with the ETB11 Connection Connection of the ARM11 MBIST Controller to the ETB11 is described in the ETB11 Implementation Guide. ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved.
Page 57 RAM B-6 ITCM data RAM B-4 Data log Failure detection 2-3 TCM valid RAM B-5 format 2-5 TLB RAM B-3 retrieval 2-4 Data seed 3-3 Bitmap mode 2-6, 3-6 ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved. Index-1...
Page 58 3-3 Timing 2-2 pattern bits 3-7 failure detection 2-3 pattern specification 3-8 instruction load 2-2 supported pattern 3-7 starting MBIST 2-3 x-Locations 3-5 y-Locations 3-5 MBRESULT A-2 Index-2 Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B...

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