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ARM PL310 Technical Reference Manual

Primecell level 2 mbist controller
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PrimeCell Level 2 MBIST Controller
(PL310)
Revision: r1p0
Technical Reference Manual
Copyright © 2007, 2008 ARM Limited. All rights reserved.
ARM DDI 0402B

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  • Page 1 PrimeCell Level 2 MBIST Controller (PL310) Revision: r1p0 Technical Reference Manual Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...
  • Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

  • Page 3: Table Of Contents

    MBIST Instruction Register About the MBIST Instruction Register ............3-2 Field descriptions ..................3-4 Appendix A Signal Descriptions MBIST controller interface signals .............. A-2 Miscellaneous signals ................. A-4 ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.
  • Page 4 Contents Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...
  • Page 5 Table 3-8 Required sums of X-address and Y-address fields for data RAM ......3-13 Table 3-9 Required sums of X-address and Y-address fields for tag RAM ......3-14 ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.
  • Page 6 Cache size field encoding ..................3-16 Table 3-13 Way size field encoding ..................3-17 Table A-1 MBIST controller interface signals ................A-2 Table A-2 Miscellaneous signals ....................A-4 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...
  • Page 7 End of bitmap data log retrieval ................2-16 Figure 3-1 MBIST Instruction Register ..................3-2 Figure 3-2 Example data RAM topology ................... 3-10 Figure 3-3 MBIST address scrambling ..................3-11 ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.
  • Page 8 List of Figures viii Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 9: Preface

    Preface This preface introduces the PrimeCell Level 2 MBIST Controller (PL310) Revision r1p0 Technical Reference Manual. It contains the following sections: • About this manual on page x • Feedback on page xiv. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 10: About This Manual

    About this manual This is the Technical Reference Manual (TRM) for the PrimeCell Level 2 MBIST Controller (PL310). In this manual the generic term MBIST controller means the PrimeCell Level 2 MBIST Controller, and cache controller means the PrimeCell Level 2 Cache Controller.
  • Page 11 Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. bold Highlights interface elements, such as menu names. Denotes ARM processor signal names. Also used for terms in descriptive lists, where appropriate. Denotes text that you can enter at the keyboard, such as monospace commands, file and program names, and source code.

  • Page 12: Key To Timing Diagram Conventions

    Denotes Advanced High-performance Bus (AHB) signals. Prefix P Denotes Advanced Peripheral Bus (APB) signals. Prefix R Denotes AXI read data channel signals. Prefix W Denotes AXI write data channel signals. Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...
  • Page 13 AMBA AXI Protocol Specification (ARM IHI 0022) • ARM Architecture Reference Manual (ARM DDI 0406) • ARM PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual (ARM DDI 0246) • ARM PrimeCell Level 2 Cache Controller (PL310) Implementation Guide (ARM DII 0045).

  • Page 14: Feedback

    Preface Feedback ARM welcomes feedback on the MBIST controller and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier giving: • the product name • a concise explanation of your comments.

  • Page 15: Introduction

    This chapter introduces the MBIST controller. It contains the following sections: • About the MBIST controller on page 1-2 • MBIST controller interface on page 1-3 • Product revisions on page 1-7. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 16: About The Mbist Controller

    Figure 1-1 shows the cache controller MBIST configuration. When MTESTON is HIGH, the MBIST block, the cache controller, and the RAMs must be clocked at the same frequency. Figure 1-1 Cache controller MBIST configuration Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 17: Mbist Controller Interface

    (ATE) and to the MBIST interface of the cache controller. Figure 1-2 MBIST controller wiring diagram Figure 1-3 on page 1-4 shows the traditional method of accessing a cache RAM for MBIST. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 18: Figure 1-3 Traditional Method Of Interfacing Mbist

    Figure 1-4 on page 1-5 shows the five pipeline stages used to access the cache RAM arrays. Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 19: Table 1-1 Cache Controller Mbist Interface Signals

    Input Global active LOW reset signal. Input Active HIGH clock signal. This clock drives the cache controller logic. MBISTDOUT[63:0] Output Data out bus from all cache RAM blocks. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.
  • Page 20 The interface of the MBIST controller communicates with both the ATE and the MBIST interface of the cache controller. See Appendix A Signal Descriptions for descriptions of the MBIST controller interface signals. See the ARM PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual for more information about the MBIST interface.

  • Page 21: Product Revisions

    This section summarizes the differences in functionality between the releases of the MBIST controller: r0p0-r1p0 The differences between these versions are: • Additional latency cycles in MBIST Instruction Register. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.
  • Page 22 Introduction Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 23: Chapter 2 Functional Description

    MBIST engine, detecting failures, and retrieving the data log. It contains the following sections: • Functional overview on page 2-2 • Functional operation on page 2-13. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 24: Functional Overview

    DATAWAIT, DATAERR, TAGWAIT, and TAGERR to 0 • set the AXI ports to 0. Figure 2-1 on page 2-3 shows the interfaces between the MBIST controller and the RAMs that MBIST tests. Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 25: Figure 2-1 Cache Controller Mbist And Ram Interfaces

    RAM. Using this nomenclature, the shortest latency is one. During functional mode, the latencies for each RAM are programmed in the cache ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 26: Table 2-1 Cache Controller Compiled Ram Latency

    13 cycles of latency. 4’b1101 14 cycles of latency. 4’b1110 15 cycles of latency. 4’b1111 16 cycles of latency. Figure 2-2 on page 2-5 shows the cache controller compiled RAM latency. Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 27: Table 2-2 Mbistaddr And Mbistdin Mapping For Data Ram, 8-Way

    MBISTDIN to data RAM mapping size indexes 128KB 4,096 DATAADDR[11:0]=MBISTADDR[18:16,10:2] DATAWD[63:0]=MBISTDIN[63:0] 256KB 8,192 DATAADDR[12:0]=MBISTADDR[18:16,11:2] DATAWD[63:0]=MBISTDIN[63:0] 512KB 16,384 DATAADDR[13:0]=MBISTADDR[18:16,12:2] DATAWD[63:0]=MBISTDIN[63:0] 32,768 DATAADDR[14:0]=MBISTADDR[18:16,13:2] DATAWD[63:0]=MBISTDIN[63:0] 65,536 DATAADDR[15:0]=MBISTADDR[18:16,14:2] DATAWD[63:0]=MBISTDIN[63:0] 131,072 DATAADDR[16:0]=MBISTADDR[18:2] DATAWD[63:0]=MBISTDIN[63:0] ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 28: Table 2-3 Mbistaddr And Mbistdin Mapping For Data Ram, 16-Way

    2-3. The signal MBISTCE[0] is for the chip enable to the data RAM. The signal MBISTDCTL[2:0] is for reads from previous MBIST transactions. Figure 2-3 on page 2-7 shows the cache controller MBIST paths for data RAM testing. Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 29: Table 2-4 Writes For Data Ram Testing

    Table 2-5 on page 2-8 shows the address range of the MBISTADDR bus used to test a tag RAM, based on the L2 cache size and configured to be 8-way. The parity for each ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 30: Table 2-5 Mbistaddr And Mbistdin Mapping For Tag Ram, 8-Way

    256KB 16KB TAGADDR[8:0]=MBISTADDR[10:2] TAGWD[20:0]=MBISTDIN[20:0] 512KB 32KB 1,024 TAGADDR[9:0]=MBISTADDR[11:2] TAGWD[20:1]=MBISTDIN[20:1] 64KB 2,048 TAGADDR[10:0]=MBISTADDR[12:2] TAGWD[20:2]=MBISTDIN[20:2] 128KB 4,096 TAGADDR[11:0]=MBISTADDR[13:2] TAGWD[20:3]=MBISTDIN[20:3] 256KB 8,192 TAGADDR[12:0]=MBISTADDR[14:2] TAGWD[20:4]=MBISTDIN[20:4] 512KB 16,384 TAGADDR[13:0]=MBISTADDR[15:2] TAGWD[20:5]=MBISTDIN[20:5] Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 31: Figure 2-4 Cache Controller Mbist Paths For Tag Ram Testing

    Only [22:0] of MBISTDIN and MBISTDOUT are used. 2.1.2 MBIST controller implementation The MBIST controller block shown in Figure 2-5 on page 2-10 consists of two major blocks: • MBIST controller • dispatch unit. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 32: Table 2-7 Mbisttx Signals

    Access sacrificial row, used during bang patterns Invert data/instruction data in Checkerboard data Write data Read data Yfast/nXfast Direction Enable bitmap mode Increment go/nogo dataword selection Latency stall control 2-10 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 33: Table 2-8 Mbistrx Signals

    MBISTRX[2:0] This signal is an output of the dispatch unit that goes to the MBIST controller. The behavior of MBISTRX[2:0] is ARM-specific and is intended for use only with the MBIST controller. The address expire signal is set when both the row and column address counters expire.
  • Page 34 At the completion of the test, the MBISTRESULT[2] signal goes HIGH. The MBISTRESULT[0] signal indicates that an address expire has occurred and enables you to measure sequential progress through the test algorithms. 2-12 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 35: Functional Operation

    60-bit shift sequence begins as shown in Figure 2-6. To enable data input from the ATE, the PLL is in bypass mode, and the clock is not running at test frequency. Figure 2-6 Loading the MBIST controller instruction ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. 2-13...

  • Page 36: Figure 2-7 Starting The Mbist Test

    Figure 2-9 on page 2-15 and Figure 2-10 on page 2-15 show the method of retrieving a data log. Note MBISTRESULT[0] is the serial data output for instructions and the data log. 2-14 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 37: Table 2-10 Data Log Format

    Failing data bits. These bits are set for faulty bits and cleared for passing bits. [3:0] The data seed used in the test. See Data seed field, MBIR[32:29] on page 3-14. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. 2-15...

  • Page 38: Figure 2-11 Start Of Bitmap Data Log Retrieval

    It always includes the doubleword select value in the least significant two bits. See Y-address and X-address fields, MBIR[36:33] and MBIR[40:37] on page 3-9 for more information on the doubleword select value. Contact ARM if you require more information.

  • Page 39: About The Mbist Instruction Register

    MBIST controller. It contains the following sections: • About the MBIST Instruction Register on page 3-2 • Field descriptions on page 3-4. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.
  • Page 40 Specifies a way size of 16KB, 32KB, 64KB, 128KB, 256KB, or 512KB. Parity support Specifies if parity is supported. Lockdown by line support Specifies if lockdown by line is supported. Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...
  • Page 41 MBIST Instruction Register Way configuration Specifies an 8-way or 16-way configuration. Field descriptions on page 3-4 describes the MBIR fields in more detail. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 42: Table 3-1 Pattern Field Encoding

    March C+ (x-fast) March C+ algorithm, incrementing X-address first b001011 March C+ (y-fast) March C+ algorithm, incrementing Y-address first b000101 Fail Pattern Tests memory failure detection capability Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...
  • Page 43 1 represents the inverse data seed • w indicates a write operation • r indicates a read operation ⇑indicates that the address is incremented • ⇓ indicates that the address is decremented. • ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 44: Table 3-2 Go/No-Go Test Pattern

    This test suite provides a comprehensive test of the arrays. The series of tests in Go/No-Go are the result of the experience in memory testing by ARM memory test engineers. Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 45: Table 3-3 Control Field Encoding

    Even if the RAM under test uses the same latency for both read and write operations, you must still program both the read latency and write latency fields of the MBIR with the same value. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 46: Table 3-4 Read Latency Field Encoding

    Table 3-5 shows the latency settings for write operations. Table 3-5 Write latency field encoding Write latency Number of cycles MBIR[48:45] per write operation b0000 b0001 b0010 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 47: Y-Address And X-Address Fields, Mbir[36:33] And Mbir[40:37]

    X-address counter and the y-address counter. One counter can be incremented or decremented only when the other counter has expired. The chosen test algorithm determines the counter that moves faster. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 48: Figure 3-2 Example Data Ram Topology

    These four bits map to the least significant bits of the Y-address counter. Because this is a data RAM, it requires two additional doubleword select bits. 3-10 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 49: Figure 3-3 Mbist Address Scrambling

    Y-address counter is the least significant bit of the column address for physical addressing of the columns. This is followed by the row address from the X-address counter and, if required, the block address. Figure 3-3 MBIST address scrambling ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. 3-11...

  • Page 50: Table 3-6 Y-Address Field Encoding

    The X-address field specifies the number of X-address counter bits to use during test. Table 3-7 shows the X address settings. Table 3-7 X-address field encoding X-address Number of MBIR[40:37] counter bits <b0010 Unsupported b0010 b0011 b0100 3-12 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 51: Table 3-8 Required Sums Of X-Address And Y-Address Fields For Data Ram

    Table 3-8 shows the required sums of the X-address and Y-address fields for testing of data RAM. Table 3-8 Required sums of X-address and Y-address fields for data RAM Cache size Data RAM 128KB 256KB 512KB ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. 3-13...

  • Page 52: Table 3-9 Required Sums Of X-Address And Y-Address Fields For Tag Ram

    The MBIST engine replicates the four bits of data 16 times to give the full 64 bits of data required on the MBISTDIN[63:0] port of the MBIST interface. 3-14 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 53: Table 3-10 Enables Field Encoding

    Tag 8 b000000010000000000 Tag 9 b000000100000000000 Tag 10 b000001000000000000 Tag 11 b000010000000000000 Tag 12 b000100000000000000 Tag 13 b001000000000000000 Tag 14 b010000000000000000 Tag 15 b100000000000000000 Data parity RAM ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. 3-15...

  • Page 54: Table 3-11 Column Width Field Encoding

    Table 3-12 shows the supported cache sizes. Table 3-12 Cache size field encoding Cache size MBIR[8:6] Cache size b000 Reserved b001 128KB b010 256KB b011 512KB b100 b101 b110 b111 3-16 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

  • Page 55: Table 3-13 Way Size Field Encoding

    Way configuration field, MBIR[0] The way configuration field specifies an 8-way or 16-way configuration in your implementation. Set to 0 for an 8-way configuration or 1 for a 16-way configuration. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. 3-17...
  • Page 56 MBIST Instruction Register 3-18 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...
  • Page 57 Signal Descriptions This appendix describes the MBIST controller signals. It contains the following sections: • MBIST controller interface signals on page A-2 • Miscellaneous signals on page A-4. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 58: Table A-1 Mbist Controller Interface Signals

    MBISTCE[13] = Tag RAM 12 chip enable MBISTCE[14] = Tag RAM 13 chip enable MBISTCE[15] = Tag RAM 14 chip enable MBISTCE[16] = Tag RAM 15 chip enable MBISTCE[17] = Data parity chip enable Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...
  • Page 59 16-way or 8-way. For a16-way configuration, connect MBISTCE[17] from the MBIST controller to MBISTCE[17] on the cache controller. For an 8-way configuration, connect MBISTCE[17] from the MBIST controller to MBISTCE[9] on the cache controller. ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved.

  • Page 60: Table A-2 Miscellaneous Signals

    MBISTDSHIFT Input Data log shift MBISTRESETN Input MBIST reset MBISTRESULT[2:0] Output Output status bus MBISTRUN Input Run MBIST test MBISTSHIFT Input Instruction shift MTESTON Input MBIST Mode Enable Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B...

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