Compaq AlphaServer ES45 Service Manual page 376

Table D–8 I_CTL Register Fields
Name Extent
SEXT(VPTB<47>) <63:48>
VPTB<47:30> <47:30>
CHIP_ID<5:0> <29:24>
BIST_FAIL <23>
TB_MB_EN <22>
MCHK_EN <21>
CALL_PAL_R23 <20>
PCT1_EN <19>
D-16 ES45 Service Guide
Type Description
RW,0 Sign extended VPTB<47>.
RW,0 Virtual Page Table Base.
RO This is a read-only field that supplies the
revision ID number for the
EV68CB/EV68DC part. EV68CB/EV68DC
pass 2.3 ID is 010111.
RO,0 Indicates the status of BIST (clear = pass,
set = fail).
RW,0
When set, the hardware ensures that the
virtual-mode loads in DTB and ITB fill flows
that access the page table and the
subsequent virtual mode load or store that
is being retried are "ordered" relative to
another processor's stores. This must be set
for multiprocessor systems in which no MB
instruction is present in the TB fill flow,
unless there are other mechanisms present
that ensure coherency.
RW,0
Machine check enable — set to enable
machine checks.
RW,0
CALL_PAL linkage register. If this bit is
one, the CALL_PAL linkage register is R23;
when zero, it is R27. Coordinate setting this
bit with SDE<1:0> to ensure that the
shadow register is used as the linkage
register.
RW,0 Enable performance counter #1. If this bit is
one, the performance counter will count if
either the system (SPCE) or process (PPCE)
performance counter enable is asserted.