Pm Control, Clock Gen - Clevo NP70PNP Service Manual

PM Control, Clock Gen

5
3.3VA 3.3VA
R829
VCCST_OVERRIDE 100K_1%_04
PCH
1.05v to 3.3v LEVEL SHIFT
D
G
PCH R831 1K_04 B
9,10 VCCST_OVERRIDE
PQ13
MMBT3904H
R838 CPU
100K_04
PCH
C
R344 *0_04 VDD3
9,51 SLP_S0#
U14
U74AHCT1G32
3.3_VCCST_OVERRIDE
R335 0_04 1 INPUT
4
SUSB# R352 0_04 2
1.8V
VDD3
U11
U74AHCT1G32
1
11,61 VCCIN_AUX_VID0
4 VCCIN_AUX_VID_0_1
2
11,61 VCCIN_AUX_VID1
1.8V
VDD3
U37
74AHC1G08GW
B
SUSB# R563 0_04 1
VCCIN_AUX_VID_0_1 2
DESIGN NOTE:
SM BUS 5VS
GND Q7A
VIA 20mil
D
MTDK3S6R
3.3VA
R277 2 G
S
1K_04
PCH
R260 PCH R287
C543
1K_04
PCH D
Q6A 5 G
S
MTDK3S6R
PCH D Q7B
MTDK3S6R D
A
2 G PCH
9,39 PM_PCH_PW ROK
S 5 G
S
Q6B
MTDK3S6R R276
PCH C539
5
4 3
3.3VS
PCH R506 *0_04
PCH C729 *0.1u_10V_X7R_04 VDD3
R828 U28A
100K_1%_04 74LVC08APW
1
PCH SUSB# PCH R510 0_04
9,35,39,49,53,56,67,72 SUSB#
3
3.3_VCCST_OVERRIDE 2
56 DDR 1.35V_PW RGD
PCH
Q44
VDD3
SM3018KW H
CPU
U28C
74LVC08APW
ALL_SYS_PW RGD 9
8
10
57 H_VR_READY
PCH R469
100K_04
PCH
VDD3
U36
74AHC1G08GW
1
51 SUSBC_EC#
4
SUSC#_PCH 2
9,51 SUSC#_PCH
CPU
VDD3
1.8V
U35
74AHC1G08GW
SUSBC_EC# 1
4
SUSB#
SUSB#_PCH
2
9,51 SUSB#_PCH
CPU
VDD3
U12
33
U74AHCT1G32
1
4
VCCST_EN 54
2 C
VIN
1.8V
ZD5231BS2
4
VCC1P8_CPU_EN 54
CPU
R562
*100K_04
CPU
SMB_DATA 7,56
PCH R261 *0_04
PCH
PCH
1K_04
3.3VS
*1u_6.3V_X5R_02
SMB_DATA_MAIN_DDR4 13,14
SMB_CLK 7,56
2021/11/9
PCH R284 *0_04
Rubband
3.3VS
PCH
PCH
1K_04
*1u_6.3V_X5R_02
SMB_CLK_MAIN_DDR4 13,14
4 3
2
VDD3
U28B
74LVC08APW PCH
4 PCH
9,39 RSMRST#
6 ALL_SYS_PW RGD_R ALL_SYS_PW RGD
R471 0_04
S0&S4_PW RGD 5
R470
10K_04
PCH
PM_PCH_PW ROK 9,39
VDD3
BUF_PLT_RST#
U28D
74LVC08APW
12
9,33 PLT_RST#
11
13
PCH
R502
100K_04
PCH
PCH R452
SUSC# 56
VDD3
PCH R491
VDD3
R434
*100K_04 U29
R486 PCH
1
9,35,39,49,53,56,67,72
100K_04
PCH 2
Q19
PCH R487 0_04 G
NV_EN_DOW N
SM3018KW H
PCH
D18
A PCH R489 430K_04 B Q14
MMBT3904H
C712 R488 PCH
PCH
51 EC_RSMRST#
PCH 100K_1%_04
PCH
CLOCK GENERATOR
C648 0.1u_6.3V_X5R_02
C628 0.1u_6.3V_X5R_02
C636 *0.1u_6.3V_X5R_02
U17
15
VDD3
V3.3A
2 9 R369 0_04
VDD3
VDD 32.768K
T73 8 6
VIOE_19.2M 19.2M
3 4
VIO_25M 25M
12
C639 12p_50V_NPO_04
NC
10 R381 330_04
VRTC
16 C654 22u_6.3V_X5R_06
X2-OUT
1 11
X1-IN NC
X2 14 R383 0_04
VOUT
C652 2.2u_6.3V_X5R_04
19001-X-016-3 SLG3NB3426VTR
6-22-25R00-1B6
PCB Footprint = TQFN16_2X3MM-GCLK
C629 12p_50V_NPO_04
XTAL 25MHz 20ppm CL<=12pF
Title Title Title
[39] PM CONTROL,CLK GEN [39] PM CONTROL,CLK GEN [39] PM CONTROL,CLK GEN
Size Size Size Document Number Document Number Document Number
A3 A3 A3 ADL-H+GN20-E3 ADL-H+GN20-E3 ADL-H+GN20-E3
Date: Date: Date: W ednesday, December 29, 2021 W ednesday, December 29, 2021 W ednesday, December 29, 2021
2
Schematic Diagrams
1
TO VR_ON & EC
ALL_SYS_PW RGD 9,36,51,57
D
C701
*0.1u_10V_X7R_04
PCH
BUF_PLT_RST# 41,44,45,47,48,50
R500
100K_04
PCH
Sheet 38 of 69
PM Control, Clock
C
Gen
1K_04
SLP_SUS# 9,40,44,51
PD
100K_04
VDD3
74AHC1G08GW PCH
4 RSMRST#
9,39 RSMRST#
B
GCLK_32K 6
T70
RTC_VBAT
VCC_RTC
2021/10/25
Rubband
A
Rev Rev Rev
6-71-NP5P0-D02 6-71-NP5P0-D02 6-71-NP5P0-D02
D02 D02 D02
Sheet Sheet Sheet 39 39 39 of of of 72 72 72
1
PM Control, Clock Gen B - 39