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Chapter 3
3.5 advanced chipset features
Advanced DRAM Control 1
Press <Enter> to enter the sub-menu and the following screen appears:
System Performance
The DRAM timing is controlled by the DRAM Timing Registers. The Timings
programmed into this register are dependent on the system design. Slower rates
may be required in certain system designs to support loose layouts or slower
memory. Setting options: Safe Mode, Normal Mode, Fast Mode, Turbo Mode,
Ultra Mode.
CAS Latency Setting
The option lets you override the SPD timing to control the CAS latency, which
determines the timing delay before SDRAM starts a read command after receiv-
ing it. Settings: 2 Clocks, 2.5 Clocks, 3 Clocks and Disabled. 2 Clocks in-
creases system performance while 3 Clocks provides more stable system
3-12
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