Panasonic FP7 Series User Manual page 117

Cpu unit
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Description
Unit memory (UM)
System data register (SD)
Index register
Timer set value register
(TS)
Timer elapsed value
32-bit
register (TE)
device
Counter set value register
(CS)
Timer/counter elapsed
value register (CE)
Master control relay (MCR)
Labels (JMP, LOOP)
Differential points (DF, DFI)
No. of step ladders
No. of subroutines
Interrupt program
Constant scan
Memory backup for power failure
Calendar timer (real-time clock)
Self-diagnosis function
Rewriting during RUN function
Security function
(Note 1)
The program capacity, data register capacity and maximum number of program blocks (PBs) vary
according to the type of CPU and memory configuration settings. They are set from the configuration
menu of tool software FPWIN GR7. The default values are pattern 3 for CPS4R* and pattern 1 for
CPS3R* and CPS2R.
Unit type
CPS4R*
CPS3R*
WUME-FP7CPUH-09
Max. 512K words per unit
110 words
15 double words (I0 to IE) (with switching function)
4,096 double words (TS0 to TS4095)
4,096 double words (TE0 to TE4095)
1,024 double words (CS0 to CS1023)
1,024 double words (CE0 to CE1023)
No limits (no numbers)
Max. 65,535 points per PB
Depending on the program capacity
No restriction
Max. 65,535 points per PB
Fixed cycle execution type PB: 1 PB per project
Execution interval: 0.1 ms or 1 ms
Interrupt from high-speed counter unit
Max. 8 points per unit, Max. 8 units per project
0 to 125 ms (adjustable in 1 ms increments)
Built-in non-volatile memory backs up the project (program,
comments and configuration data) and operation memory.
(Excluding calendar timer)
Yes (a separately sold backup battery is required)
Watchdog timer, program syntax check
Yes (rewriting on a PB basis, no limit to the number of rewriting
steps)
Password function, no-read settings, encryption
can be set for the program, comments and configuration data
Memory type
Program capacity (step)
Data register capacity
(word)
Maximum number of PBs
Program capacity (step)
8.1 CPU Unit Specifications
Rated voltage
(Note 4)
Memory select pattern
1
2
234,000
221,500
65,536
131,072
468
443
121,500
96,000
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 5)
3
4
196,000
144,500
262,144
524,288
392
289
64,000
32,000
5
51,500
999,424
103
8-5

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