NELLCOR PURITAN BENNETT Symphony N-3000 Service Manual page 106

Technical Supplement
S- 16
c. RAM Memory
The U5 RAM chip provides the SpO
memory. The U1 CS0 provides the chip enable signal for U3.
The U3 hardware has an 8-bit wide data path. After boot up, CS0 is
configured as a chip select with a start address of 40000h, block length of
128K, 8-bit port, both bytes access, both read and write access, and gated
with AS. This configuration gives a data memory range of 40000 through
5FFFF.
The number of wait states to generate depends upon the U1 clock speed and
the U3 access speed. The number of wait states for CS0 is set to 0, based on a
U3 access time of 85ns, minimum.
d. Stackbus
The SpO controller board also communicates with other boards within the
2
N-3000 via the stackbus. The stackbus is controlled by the COM 20020
Arcnet controller chip, U6, which is enabled by U1 CS1.
CS1 must be configured as a chip select with a start address of 60000h, block
length of 2k, 8-bit port, both bytes access, both read and write access, and
gated with AS. This configuration maps the stackbus in the memory range of
60000h through 607FFh.
The number of wait states to generate depends on the U1 clock speed. The
number of wait states for CS1 must be set to 2, based upon a CPU clock speed
of 16.0 MHz.
e. Programmable Clock
The clock frequency on the SpO
software. The clock signal is labeled CTRL_CLK. The clock circuitry consists
of U7 and U10. One half of U7 takes a 20 MHz input and produces three
output frequencies: 10 MHz, 2.5 MHz, and 1.25 MHz. The 10 MHz frequency
is the clock rate of the programmable down counter, U10. The second half of
U7 takes the terminal count (TC) output of U10 and converts it to a 50% duty
cycle square wave.
The frequency of CTRL_CLK is controlled by an 8-bit number. The bits of this
number are split between two output ports. The lower 5 bits of the number
are programmed on the lower 5 bits of port C. The upper 3 bits of the number
are programmed on the upper 3 bits of port E.
The formula for the CTRL_CLK frequency is: frequency = 5MHz/ (1 + TIME),
where TIME is the 8-bit number output by the CPU. TIME has a valid range
of 1-255. The circuit provides an adjustment range of 19.531 kHz to 2.5 MHz.
The CTRL_CLK signal is input back to U1 Pin 16. During the POST routine,
this pin is used to monitor the programmable clock hardware output to verify
performance.
f. Intermodule Connector
The SpO controller board is connected to the UIF board via the J1
2
intermodule connector. The UIF board provides power to the SpO
Stackbus and module synchronization lines are also routed through J1.
Controller board with 128K bytes of
2
controller board is programmed via
2
controller.
2