NELLCOR PURITAN BENNETT Symphony N-3000 Service Manual page 100

Technical Supplement
S- 10
The PROM chip select is connected to the /CSBOOT signal (Pin 112) of U3. At
system reset, this signal defaults to decode address %00000 for a block of 1
megabyte, held active for 13 wait states and gated with the processor address
strobe. The output enable of the PROM (pin 22) is connected to ground
through R8 to allow data to be gated onto the data bus as soon as the
/CSBOOT signal goes active. After a system reset, /CSBOOT is configured to
have one wait state and to be active only for the address range of the PROM.
Processor RAM (U13 and U23)— The RAMs are used by the processor to
store program variables, values and trend data. Each is 128K x 8, arranged to
provide 128K x 16 bits of RAM for use by the processor. U3 address lines A17
through A1 are connected to both RAMs' address lines A16 through A0. U3
data bus lines D15 through D8 are connected to U13 data bus lines D7
through D0 for the upper 8 bits of data. U3 data bus lines D7 through D0 are
connected to U23 data bus lines D7 through D0 for the lower 8 bits of data.
The active low chip select inputs of U13 and U23 are connected to the CS0
and CS1 chip select outputs of U3. The active high chip select inputs of U13
and U23 are connected to the active low system reset to prevent writing to
the RAM while the system power is coming on or while the watchdog reset is
active. The output enables of U13 and U23 are connected to digital ground.
The write enable inputs of U13 and U23 are connected to the data direction
(R/-W) output of U3. At system reset, the RAM chips are disabled and CS0
and CS1 from U3 are disabled. After system reset, CS0 and CS1 are
configured to be gated with data strobe output DS from U3.
When the N-3000 is in STANDBY, RAM power is supplied by the backup
battery output of the BQ2001. Power is maintained by the N-3000 lead-acid
battery and, in the event that the lead-acid battery becomes discharged or is
removed, by the lithium backup battery BT1.
Arcnet controller — U6 is the Arcnet controller (COM20020). It is used by
the processor to implement the stackbus protocol. It is an 8-bit, memory-
mapped device that manages the stackbus communications physical
implementation along with the stackbus adapter. It is connected to the upper
8 bits of the processor data bus to allow for byte operations from the
processor. The chip select for U6 is processor pin /CS4.
Digital to Analog Converter — DAC U5 is an 8-bit converter used by the
processor to control speaker volume. It is a write-only, memory-mapped
peripheral connected to the upper 8 bits (D15 through D8) of the processor
data bus. It converts the 8-bit data value written into it by the processor to
control the amplitude of the square wave generated by processor output OC2.
The resultant amplitude controlled square wave is then sent to audio
amplifier U4 to drive the 8-ohm speaker. The chip select for U5 is processor
pin /CS5.
Analog to Digital Converter — ADC U27 is an 8-bit analog to digital
converter used by the processor to measure three different analog voltages. It
is a read-only, memory-mapped peripheral connected to the upper 8 bits (D15
through D8) of the processor data bus. The analog voltage values indicate
which display board button has been pressed, what the combined voltage of
both lithium batteries is, and the value of the analog voltage being supplied
from transistor Q10 to the SpO2 module and 5V regulator chips (U17 and
U18). The chip select for U5 is processor pin /CS7. The selection of analog
voltages to read is controlled by processor outputs PWMA and PWMB which
must be set up prior to accessing U27.