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TQ TQMa8MxML User Manual

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TQMa8MxML & TQMa8MxNL
User's Manual
TQMa8MxML UM 0103
04.07.2022

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Summary of Contents for TQ TQMa8MxML

  • Page 1 TQMa8MxML & TQMa8MxNL User's Manual TQMa8MxML UM 0103 04.07.2022...

  • Page 2: Table Of Contents

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page I TABLE OF CONTENTS ABOUT THIS MANUAL ...................................... 1 Copyright and license expenses .................................. 1 Registered trademarks ....................................1 Disclaimer ..........................................1 Imprint ........................................... 1 Tips on safety ........................................2 Symbols and typographic conventions ..............................
  • Page 3 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page II 3.2.7 Reset ............................................ 42 3.2.8 Differences between TQMa8MxML and TQMa8MxNL ........................43 3.2.8.1 CPU ............................................43 3.2.8.2 SDRAM ..........................................43 3.2.8.3 Boot Mode ........................................43 3.2.8.4 SAI ............................................43 3.2.8.5...
  • Page 4 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page III TABLE DIRECTORY Table 1: Terms and conventions ....................................2 Pinout TQMa8MxML, top view through TQMa8MxML ........................7 Table 2: Table 3: TQMa8MxML, signals ....................................... 8 Pinout TQMa8MxNL, top view through TQMa8MxNL ........................13...
  • Page 5 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page IV FIGURE DIRECTORY Figure 1: Block diagram i.MX 8M Mini ..................................5 Figure 2: Block diagram i.MX 8M Nano ..................................5 Figure 3: Block diagram TQMa8MxML / TQMa8MxNL (simplified) ........................6 Figure 4: Block diagram QSPI NOR Flash interface ...............................
  • Page 6 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page V REVISION HISTORY Rev. Date Name Pos. Modification 0100 20.02.2021 Petz First issue Non-functional changes, expressions, formatting 0101 04.05.2021 Petz 3.2.5.15 Information regarding pull-ups added Table 37 Values added 0102 27.10.2021...

  • Page 7: About This Manual

    User's Manual, or due to usage of erroneous or incomplete information, are exempted, as long as there is no proven intentional or negligent fault of TQ-Systems GmbH. TQ-Systems GmbH explicitly reserves the rights to change or add to the contents of this User's Manual or parts of it without special notification.

  • Page 8: Tips On Safety

    Handling and ESD tips General handling of your TQ-products The TQ-product may only be used and serviced by certified personnel who have taken note of the information, the safety regulations in this document and all related rules and regulations. A general rule is not to touch the TQ-product during operation. This is especially important when switching on, changing jumper settings or connecting other devices without ensuring beforehand that the power supply of the system has been switched off.

  • Page 9: Naming Of Signals

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 3 Naming of signals A hash mark (#) at the end of the signal name indicates a low-active signal. Example: RESET# If a signal can switch between two functions and if this is noted in the name of the signal, the low-active function is marked with a hash mark and shown at the end.

  • Page 10: Brief Description

    The TQMa8MxML extends the TQ-Systems GmbH product range and offers an outstanding computing performance. All essential i.MX 8M Mini pins are routed to the TQMa8MxML LGA pads. There are therefore no restrictions for customers using the TQMa8MxML with respect to an integrated customised design. All essential components like CPU, LPDDR4, eMMC, and PMIC are already integrated on the TQMa8MxML.

  • Page 11: Cpu Block Diagrams

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 5 CPU block diagrams Figure 1: Block diagram i.MX 8M Mini (Source: NXP) Figure 2: Block diagram i.MX 8M Nano (Source: NXP)

  • Page 12: Electronics

    The multiple pin configurations by different i.MX 8M Mini/Nano-internal function units must be taken note of. The pin assignment in Table 3 refers to a TQMa8MxML with i.MX 8M Mini Quad CPU in combination with the Starterkit MBa8Mx. The pin assignment in Table 5 refers to a TQMa8MxNL with i.MX 8M Nano Quad CPU in combination with the Starterkit MBa8Mx.

  • Page 13: Pinout Tqma8Mxml

    3.1.1.1 Pinout TQMa8MxML The TQMa8MxML has a total of 281 LGA pads. The TQMa8MxML is soldered and thus permanently connected to the carrier board. It is not trivial and it is not recommended to remove the TQMa8MxML. The following table shows the TQMa8MxML pad-out, top view through the TQMa8MxML.

  • Page 14: Tqma8Mxml Signals

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 8 3.1.1.2 TQMa8MxML signals Details about the electrical characteristics of single pins and interfaces are to be taken from the i.MX 8M Mini documentation (1), (3), (5), as well as the PMIC Data Sheet (7).
  • Page 15 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 9 3.1.1.2 TQMa8MxML signals (continued) Table 3: TQMa8MxML, signals (continued) CPU ball Signal Group Dir. Level TQMa8MxML pad AG14 GPIO1_IO00 GPIO 3.3 V AF14 GPIO1_IO01 GPIO 3.3 V...
  • Page 16 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 10 3.1.1.2 TQMa8MxML signals (continued) Table 3: TQMa8MxML, signals (continued) CPU ball Signal Group Dir. Level TQMa8MxML pad A5, A8, A11, A14, A16, B2, B5, B7, B10, B17, C5, C6, C8, C11, C15, C16, C18, D3, D4, D5, D6, D7, D9, D12, D14, D17, E2, E3, E4, E5, E8, E10, E13, E15, E19, F3, F4, F5, F11, –...
  • Page 17 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 11 3.1.1.2 TQMa8MxML signals (continued) Table 3: TQMa8MxML, signals (continued) CPU ball Signal Group Dir. Level TQMa8MxML pad AB18 SAI1_MCLK 3.3 V AF16 SAI1_RXC 3.3 V AG15 SAI1_RXD0 3.3 V...
  • Page 18 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 12 3.1.1.2 TQMa8MxML signals (continued) Table 3: TQMa8MxML, signals (continued) CPU ball Signal Group Dir. Level TQMa8MxML pad QSPI_A_DATA0 QSPI 1.8 V QSPI_A_DATA1 QSPI 1.8 V QSPI_A_DATA2 QSPI 1.8 V...

  • Page 19: Pinout Tqma8Mxnl

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 13 3.1.1.3 Pinout TQMa8MxNL The TQMa8MxNL has a total of 281 LGA pads. The TQMa8MxNL is soldered and thus permanently connected to the carrier board. It is not trivial and it is not recommended to remove the TQMa8MxNL.

  • Page 20: Tqma8Mxnl Signals

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 14 3.1.1.4 TQMa8MxNL signals Details about the electrical characteristics of single pins and interfaces are to be taken from the i.MX 8M Nano documentation (2), (4), (6), as well as the PMIC Data Sheet (7).
  • Page 21 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 15 3.1.1.4 TQMa8MxNL signals (continued) Table 5: TQMa8MxNL, signals (continued) CPU ball Signal Group Dir. Level TQMa8MxNL pad AG14 GPIO1_IO00 GPIO 3.3 V AF14 GPIO1_IO01 GPIO 3.3 V...
  • Page 22 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 16 3.1.1.4 TQMa8MxNL signals (continued) Table 5: TQMa8MxNL, signals (continued) CPU ball Signal Group Dir. Level TQMa8MxNL pad A5, A8, A11, A14, A16, B2, B5, B7, B10, B17, C5, C6, C8, C11, C15, C16, C18, D3, D4, D5, D6, D7, D9, D12, D14, D17, E2, E3, E4, E5, E8, E10, E13, E15, E19, F3, F4, F5, F11, –...
  • Page 23 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 17 3.1.1.4 TQMa8MxNL signals (continued) Table 5: TQMa8MxNL, signals (continued) CPU ball Signal Group Dir. Level TQMa8MxNL pad AA26 SD2_CD# 1.8 / 3.3 V SD2_CLK 1.8 / 3.3 V SD2_CMD 1.8 / 3.3 V...

  • Page 24: Differences Between Tqma8Mxml And Tqma8Mxnl

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 18 3.1.1.5 Differences between TQMa8MxML and TQMa8MxNL The following table shows the differences between TQMa8MxML and TQMa8MxNL. Table 6: Differences between TQMa8MxML and TQMa8MxNL CPU ball Module pad...

  • Page 25: System Components

    3.2.1 i.MX 8M Mini and i.MX 8M Nano derivatives 3.2.1.1 i.MX 8M Mini derivatives Depending on the TQMa8MxML version, one of the following i.MX 8M Mini derivatives is assembled. Table 7: i.MX 8M Mini derivatives TQMa8MxML version i.MX 8M Mini derivative i.MX 8M Mini clock...

  • Page 26: Boot Modes

    Boot configuration i.MX 8M Mini The i.MX 8M Mini uses two BOOT_MODE pins, which are available on the TQMa8MxML's LGA pads. These require pull-up or pull-down wiring to 3.3 V and Ground. The pull-up voltage used must be stable before the release of IMX_POR.

  • Page 27: Boot Device Emmc

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 21 3.2.1.6.1 Boot device eMMC Table 12: Boot configuration eMMC at USDHC3 Fuse Signal TQMa8MxML Setting BOOT_CFG14 SAI1_TXD6 Boot Device: BOOT_CFG13 SAI1_TXD5 010: MMC/eMMC BOOT_CFG12 SAI1_TXD4 Port Selection:...

  • Page 28: Boot Device Sd Card

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 22 3.2.1.6.2 Boot device SD card Table 13: Boot configuration SD card at USDHC2 Fuse Signal TQMa8MxML Setting BOOT_CFG14 SAI1_TXD6 Boot Device: BOOT_CFG13 SAI1_TXD5 001: SD/eSD BOOT_CFG12 SAI1_TXD4...

  • Page 29: Boot Configuration I.mx 8M Nano

    3.2.2.2 eMMC NAND Flash An eMMC NAND Flash is provided on the TQMa8MxML for boot loader and application software. The eMMC is connected to the i.MX 8M Mini via USDHC3. The i.MX 8M Mini and i.MX 8M Nano support transfer modes up to the current eMMC standard v5.1 according to JESD84-B51.

  • Page 30: Qspi Nor Flash

    QSPI NOR Flash The i.MX 8M Mini has two QSPI interfaces, of which QSPI_A is occupied on the TQMa8MxML when QSPI NOR Flash is populated. If no QSPI NOR Flash is populated on the TQMa8MxML, the QSPI_A interface signals can be used on the carrier board.

  • Page 31: Trust Secure Element Se050

    Trust Secure Element SE050 As an option, a Trust Secure Element NXP SE050 can be assembled on the TQMa8MxML. The SE050 is connected to the I2C1 bus. The ISO14443 signals are routed to the I2C4 interface, which is no longer available in this case.

  • Page 32: Rtc

    Discrete RTC PCF85063A In addition to the i.MX 8M Mini-internal RTC the TQMa8MxML provides a discrete RTC PCF85063A, which is connected to I2C1. The quartz used to clock the RTC has a standard frequency tolerance of ±20 ppm @ +25 °C.

  • Page 33: Interfaces

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 27 3.2.5 Interfaces 3.2.5.1 Overview The following interfaces or signals are not available on the TQMa8MxML LGA pads and are used on the TQMa8MxML. Table 18: Internal interfaces Interface Chapter Remark USDHC3 3.2.2.2...

  • Page 34: Gpio

    Page 28 3.2.5.3 GPIO Except for the dedicated differential signals, e.g., MIPI DSI/CSI, and USB, all CPU signals routed to the TQMa8MxML LGA pads can be configured as GPIO. The following table shows the GPIO signals primarily configured as GPIO.

  • Page 35: I 2 C

    C interfaces provided by the i.MX 8M Mini are routed to TQMa8MxML LGA pads. All I C devices on the TQMa8MxML are connected to I2C1. If more devices are connected to the I2C1 bus on the carrier board, the maximum capacitive bus load according to the I C standard has to be taken note of.

  • Page 36: Jtag

    JTAG On the TQMa8MxML JTAG_TRST# is available for the JTAG interface. On the TQMa8MxNL, JTAG_TRST# is used as BOOT_MODE2 and is therefore not available in the JTAG interface. In this case an external pull circuit must be provided on the carrier board for this signal to enable the setting of the different Boot Modes.

  • Page 37: Mipi Csi

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 31 3.2.5.6 MIPI CSI The i.MX 8M Mini provides a MIPI-CSI camera interface. Up to 1.5 Gbps are transmitted on four data pairs. Image formats up to 4K @ 30 fps are supported.

  • Page 38: Mipi Dsi

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 32 3.2.5.7 MIPI DSI The i.MX 8M Mini provides a DSI interface to output serial display data. The MIPI-DSI PHY supports resolutions up to 1080p @ 60 fps.

  • Page 39: Pcie

    The i.MX 8M Mini provides one PCIe 2.0 lane, the i.MX 8M Nano does not provide this feature. The 100 MHz reference clock can be generated on the TQMa8MxML and output to PCIE_REF_CLKN/P for the PCIe card. The 100 MHz reference clock can be generated internally and output to PCIE_REF_CLKN/P for the PCIe card.

  • Page 40: Sai

    S, AC97, TDM and other codecs are supported, but they have to be implemented on the carrier board. The supply voltage of all SAI interfaces is set to 3.3 V by the TQMa8MxML. The i.MX 8M Nano does not provide the SAI1 interface. Therefore, external signal termination is required for TQMa8MxNL modules.
  • Page 41 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 35 3.2.5.9 SAI (continued) The following table shows the signals used by the SAI interface. Table 27: SAI signals Signal Direction CPU ball TQMa8MxML TQMa8MxNL Power group SAI1_MCLK...

  • Page 42: Spdif

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 36 3.2.5.10 SPDIF The i.MX 8M Mini provides an SPDIF interface, which is routed to the TQMa8MxML LGA pads. i.MX 8M Mini / Nano SPDIF_RX SPDIF_RX SPDIF_TX SPDIF_TX...

  • Page 43: Ecspi

    The SPI interfaces of the i.MX 8M Mini are full-duplex capable and support both master and slave modes. As a primary function, the ECSPI1 and ECSPI2 interfaces each have a chip select on TQMa8MxML LGA pads. ECSPI3 can be multiplexed to UART pads.

  • Page 44: Uart

    3.2.5.13 UART The i.MX 8M Mini provides four UART interfaces, which are all routed to TQMa8MxML LGA pads. UART2 can be used to debug the A53 core, UART4 can be used to debug the M4 core. The voltage supply must be set to 1.8 V or 3.3 V via LGA pad V_UART.

  • Page 45: Usb

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 39 3.2.5.14 The i.MX 8M Mini provides two USB 2.0 controllers (including USB 2.0 OTG). USB1 is configured as USB OTG by default. The OTG signals use GPIO1 pins as shown in the block diagram.

  • Page 46: Usdhc (Sd Card)

    SD2_RST# AB26 SD2_WP AA27 V_3V3_SD – V_3V3_SD The voltage level of the data signals between SD card and CPU is controlled by the signal SD2_VSELECT on the TQMa8MxML. Table 33: SD2_VSELECT logic SD2_VSELECT SD card voltage High 1.8 V 3.3 V...

  • Page 47: External Clock Sources

    External clock sources The i.MX 8M Mini has the option to use two external oscillators as clock sources. All four CPU balls provided for this purpose are connected to TQMa8MxML LGA pads. The following table shows these clock signals. Table 34: XTAL signals...

  • Page 48: Reset

    V_1V8_SNVS RTC_RESET# RESET_OUT# POR# PMIC_RST# PMIC_RST# Figure 21: Block diagram Reset The following table describes the reset signals available at the TQMa8MxML LGA pads: Table 36: Reset signals Signal Direction TQMa8MxML Power group Remark Reset input of i.MX 8M Mini •...

  • Page 49: Differences Between Tqma8Mxml And Tqma8Mxnl

    • The i.MX 8M Nano does not have a VPU and therefore cannot support video processing. Due to the omission of the VPU, the TQMa8MxNL consumes less power than the TQMa8MxML. • The "Non Maskable Interrupt" (NMI) can still be used on the TQMa8MxNL.

  • Page 50: Power

    The power consumption strongly depends on the application, the mode of operation and the operating system. For more information on power consumption and savings options, see NXP Application Note AN12410 (10) and AN12269 . The following table shows the TQMa8MxML and TQMa8MxNL current and power consumptions at 5 V (±5 %) supply voltage: Table 37:...

  • Page 51: Voltage Monitoring

    The TQMa8MxML features a supervisor which monitors the input voltage (V If the input voltage drops below 4.38 V, a Reset is triggered and the TQMa8MxML is held in reset until the input voltage is in the permitted range again.

  • Page 52: I/O Voltages

    If not set, the corresponding TQMa8MxML I/O signals are not supplied with voltage. The TQMa8MxML supply outputs V_1V8 or V_3V3 can be used for this purpose. If 2.5 V is to be used, this voltage must be provided by the carrier board, since it cannot be provided by the TQMa8MxML.

  • Page 53: Pmic

    PMIC_WDOG# Figure 24: Block diagram PMIC interface C address 0x25 / 010 0101b The PMIC has I  The following PMIC and power management signals are available on the TQMa8MxML LGA pads Table 40: PMIC signals Signal Direction TQMa8MxML Power group Remark Watchdog Reset input of i.MX 8M Mini...

  • Page 54: Impedances

    By default, all single-ended signals have a nominal impedance of 50 Ω ±10 %. However, some interfaces on the TQMa8MxML are routed with different impedances, depending on the signal requirements. The following table is taken from the Hardware Developer's Guide (6) and shows the respective interfaces:...

  • Page 55: Mechanics

    Highest component, top side 0.57 mm ±0.2 mm Highest component, bottom side 3 mm ±0.2 mm Top edge CPU with soldered TQMa8MxML. Referenced to top edge of carrier board. Figure 27: TQMa8MxML dimensions, bottom view Figure 26: TQMa8MxML dimensions, top view...

  • Page 56: Component Placement

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 50 Component placement Figure 28: TQMa8MxML, component placement top The labels on the TQMa8MxML show the following information: Table 43: Labels on TQMa8MxML Label Content TQMa8MxML version and revision...

  • Page 57: Adaptation To The Environment

    Structural requirements The TQMa8MxML has to be soldered on the carrier board. To ensure a high-quality connection of the LGA pads during reflow soldering of the TQMa8MxML, the LGA pads must be free of grease and dirt.

  • Page 58: Safety Requirements And Protective Regulations

    Page 52 SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS The TQMa8MxML was developed according to the requirements of electromagnetic compatibility (EMC). Depending on the target system, anti-interference measures may still be necessary to guarantee the adherence to the limits for the overall system.

  • Page 59: Climate And Operational Conditions

    Reliability and service life The MTBF calculated for the TQMa8MxML is 1,270,405 hours with a constant error rate @ +40 °C, Ground Benign. The TQMa8MxML is designed to be insensitive to shock and vibration. The TQMa8MxML must be assembled in accordance with the processing instructions provided by TQ-Systems GmbH.

  • Page 60: Environment Protection

    By environmentally friendly processes, production equipment and products, we contribute to the protection of our environment. To be able to reuse the TQMa8MxML, it is produced in such a way (a modular construction) that it can be easily repaired and disassembled. The energy consumption of this subassembly is minimised by suitable measures.

  • Page 61: Appendix

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 55 APPENDIX Acronyms and definitions The following acronyms and abbreviations are used in this document: Table 46: Acronyms Acronym Meaning ® Advanced RISC Machine Ball Grid Array BIOS...
  • Page 62 User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 56 Acronyms and definitions (continued) Table 46: Acronyms (continued) Acronym Meaning Printed Circuit Board PCIe Peripheral Component Interconnect Express PCMCIA People Can't Memorize Computer Industry Acronyms Pull-Down (resistor)

  • Page 63: References

    User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 57 References Table 47: Further applicable documents Name Rev., Date Company i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 15 Jan 2021 i.MX 8M Nano Applications Processor Reference Manual Rev.
  • Page 64 TQ-Systems GmbH Mühlstraße 2 l Gut Delling l 82229 Seefeld Info@TQ-Group TQ-Group...

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