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Exar XRT73L04B Manual

4 channel ds3/e3/sts-1 line interface unit
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OCTOBER 2003
GENERAL DESCRIPTION
The XRT73L04B, 4-Channel, DS3/E3/STS-1 Line In-
terface Unit is a low power CMOS version of the
XRT73L04A and consists of four independent line
transmitters and receivers integrated on a single chip
designed for DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73L04B can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configured to operate in a mode/data
rate that is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73L04B performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
F
1. XRT73L04B B
IGURE
E3_(n)
RTIP_(n)
RRing_(n)
REQEN_(n)
LOSTHR
SDI
SDO
SClk
CS/(SR/DR)
REGR
TTIP_(n)
TRing_(n)
MTIP_(n)
MRing_(n)
DMO_(n)
Notes: 1. (n) = 0, 1, 2 , or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
D
LOCK
IAGRAM
STS-1/DS3_(n)
Host/(HW)
RLOL_(n) EXClk_(n)
AGC/
Slicer
Equalizer
Peak
Detector
LOS Detector
Serial
Processor
Loop MUX
Interface
HDB3/
Pulse
B3ZS
Shaping
Encoder
Tx
Device
Control
Monitor
FEATURES
• Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L04A
• Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
• Contains a 4-Wire Microprocessor Serial Interface
• Full Loop-Back Capability
• Transmit and Receive Power Down Modes
• Full Redundancy Support
• Uses Minimum External components
• Single +3.3V Power Supply
• Low Power CMOS design
• 5V tolerant I/O
• -40°C to +85°C Operating Temperature Range
• Available in a Thermally Enhanced 144 pin LQFP
package
APPLICATIONS
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
• Multiplexers
• ATM Switches
RxOFF
RxClkINV
Clock
Invert
Recovery
Data
HDB3/
Recovery
B3ZS
Decoder
Transmit
Logic
Duty Cycle Adjust
Channel 0
Channel 1
Channel 2
Channel 3
•
•
(510) 668-7000
FAX (510) 668-7017
XRT73L04B
REV. 1.0.1
RxClk_(n)
RPOS_(n)
RNEG_(n)/
(LCV_(n))
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF
•
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Summary of Contents for Exar XRT73L04B

  • Page 1 DS3, E3 or SONET STS-1 applications. • Contains a 4-Wire Microprocessor Serial Interface Each channel of the XRT73L04B can be configured • Full Loop-Back Capability to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) • Transmit and Receive Power Down Modes or the SONET STS-1 (51.84 Mbps) rates.
  • Page 2 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TYPICAL APPLICATIONS 2. M ATM A IGURE ULTI HANNEL PPLICATION RPOS RPOS RPOS RRPOS RTIP RNEG RNEG RNEG RRNEG RRing RxClk RxClk RxLineClk RRClk Switch/ XRT74L74 XRT71D04 XRT73L04B MClk TPOS TTIP...
  • Page 3 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 4. P XRT73L04B 144 P TQFP IGURE IN OUT OF THE IN THE PACKAGE AGND_2 SDO/E3_0 REGR/(RxClkINV) SDI/E3_1 LOSMUTEN SClk/(RxOFF) AGND_3 CS/(SR/DR) RLOL_3 RLOL_1 RLOS_3 RLOS_1 EXClk_2 EXClk_0 RLOL_2 RLOL_0 RLOS_2...

  • Page 4: Table Of Contents

    HANNELS 0, 1, 2 3 ..................24 ECEIVE ECTION HANNELS ....................24 ICROPROCESSOR ERIAL NTERFACE Table 1:Role of Microprocessor Serial Interface pins when the XRT73L04B is operating in the Hardware Mode Figure 13.Functional Block Diagram of the XRT73L04B ................25...

  • Page 5: General Description Features Applications

    XRT73L04B ........33 NTERFACING THE RANSMIT ECTIONS OF THE TO THE Figure 21.Recommended Schematic for Interfacing the Transmit Section of the XRT73L04B to the Line ..33 ....................34 RANSFORMER ECOMMENDATIONS 3.0 THE RECEIVE SECTION ......................... 35 3.1 I XRT73L04B ........

  • Page 6: Typical Applications

    Figure 31.The typical interface for the Transmission of Data in a Single-Rail Format from the Receive Section of the XRT73L04B to the Receiving Terminal Equipment ..............45 Figure 32.The behavior of the RPOS and RxClk output signals while the XRT73L04B is transmitting Single-Rail data to the Receiving Terminal Equipment ..................46 3.7 S...

  • Page 7: Ordering Information

    ESCRIPTION OF THE OMMAND EGISTERS CR1-( ) ......................51 OMMAND EGISTER Table 7:Hexadecimal Addresses and Bit Formats of XRT73L04B Command Registers ....... 52 5.2 D ............53 ESCRIPTION OF IELDS FOR EACH OMMAND EGISTER Command Register - CR0-(n) ......................53 ) ......................

  • Page 8: Pin Descriptions ( By Function )

    TxClk_(n). TPData_0 Transmit Positive Data Input - Channel (n) TPData_1 The XRT73L04B samples this pin on the falling edge of TxClk_(n). If the TPData_2 device samples a "1", then it generates and transmits a positive polarity TPData_3 pulse to the line.
  • Page 9 The XRT73L04B is configured to operate in either the DS3 or SONET STS-1 Modes. b. The XRT73L04B is configured to operate in the Hardware Mode. : This pin to should be tied to GND if the XRT73L04B is going to be operating in the HOST Mode, (internally pulled-down). TxOFF Transmitter OFF Input: Setting this input pin "High"...

  • Page 10: Receive Interface

    XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 RECEIVE INTERFACE ESCRIPTION RxClk_0 Receive Clock Output - Channel (n): RxClk_1 This output pin is the Recovered Clock signal from the incoming line sig- RxClk_2 nal for Channel (n). The Receive Section of Channel (n) outputs data via...

  • Page 11: Clock Interface

    Equalizer. The guidelines for enabling and disabling the Receive Equal- izer are described in Section 3.2. : This pin is ignored and should be tied to GND if the XRT73L04B is going to be operating in the HOST Mode, (internally pulled-down).

  • Page 12: Operating Mode Select

    The XRT73L04B ignores this pin if the E3_(n) pin is set to "1". STS1/DS3_3 This input pin is ignored if the XRT73L04B is operating in the HOST Mode. : This pin should be tied to GND if the XRT73L04B is going to be operating in the HOST Mode, (internally pulled-down).

  • Page 13: Control And Alarm Interface

    The frequency of this "1’s" pattern is determined by TxClk_(n). This input pin is ignored if the XRT73L04B is operating in the HOST Mode. : This pin should be tied to GND if the XRT73L04B is going to be operating in the HOST Mode, (internally pulled-down). RLOS_0...
  • Page 14 A "High" on this pin with RLB_(n) also being set to "High" configures Channel (n) to operate in the Digital Local Loop-Back Mode. : This pin is ignored and should be tied to GND if the XRT73L04B is going to be operating in the HOST Mode.

  • Page 15: Microprocessor Interface

    LOSMUTEN MUTE-upon-LOS Enable Input (Hardware Mode): This input pin is use to configure the XRT73L04B, while it is operating in the Hardware Mode, to MUTE the recovered data via the RPOS_(n), RNEG_(n) output pins whenever one of the Channels declares an LOS conditions.
  • Page 16 The function of this pin depends upon the mode of operation.In Hard- ware mode, this pin functions as RxClkINV. HOST Mode - Register Reset Input: Setting this input pin "Low" causes the XRT73L04B to reset the contents of the Command Registers to their default settings and to its default operating configuration.

  • Page 17: Power And Ground Pins

    XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 POWER AND GROUND PINS PIN # NAME TYPE DESCRIPTION TxAVDD_2 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) TxAGND_2 **** Transmitter Analog Ground - Channel(n) TxAVDD_3 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n)

  • Page 18: No Connection Pins

    XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 POWER AND GROUND PINS PIN # NAME TYPE DESCRIPTION RxDGND_3 **** Receiver Digital Ground - Channel(n) RxDVDD_3 **** Receiver Digital Supply 3.3V + 5% - Channel (n) EXDGNDA **** External Clock Digital Ground...

  • Page 19: Electrical Characteristics

    24° C/W Theta-JC 5.5° C/W : The XRT73L04B is assembled in a thermally Ground connections of the device. This Heat Slug can be enhanced package with an integral Copper Heat Slug. The soldered to the mounting board if desired, but must be elec-...

  • Page 20: Ac Electrical Characteristics (See Figure 5)

    RxClk_(n) Clock Rise Time (10% to 90%) RxClk_(n) Clock Fall Time (10% to 90%) Input Capacitance Load Capacitance 2. All XRT73L04B digital outputs are also TTL 5V OTES compliant. However, these outputs will not drive to 1. All XRT73L04B digital inputs are designed to be 5V nor will they accept external 5V pull-ups.
  • Page 21 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 5. T E3, DS3 STS-1 R IGURE RANSMIT ULSE MPLITUDE IRCUIT FOR ATES TYPICAL CHANNEL TTIP_(n) 31.6Ω Channel (n) Channel (n) TxPOS_(n) TPData_(n) TxNEG_(n) TNData_(n) 75Ω TxLineClk_(n) TxClk_(n) 31.6Ω TRing_(n) Only One Channel Shown 6.

  • Page 22: Line Side Parameters E3 Application

    XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED E3 A ARAMETERS PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS Transmit Output Pulse Amplitude 0.90...

  • Page 23: Line Side Parameters Sonet Sts-1 Application

    XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED STS-1 A ARAMETERS ONET PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS Transmit Output Pulse Amplitude (Measured with TxLEV=0) 0.65...

  • Page 24: Line Side Parameters Ds3 Application

    XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED DS3 A ARAMETERS PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS Transmit Output Pulse Amplitude (Measured at 0 feet, TxLEV=0) 0.65...
  • Page 25 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 Figure 8, Figure 9 and Figure 10 present the Pulse Template requirements for the E3, DS3 and STS-1 Rates. 8. ITU-T G.703 T E3 A IGURE RANSMIT UTPUT ULSE EMPLATE FOR...
  • Page 26 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 10. B GR-253-CORE T SONET STS-1 A IGURE ELLCORE RANSMIT UTPUT ULSE EMPLATE FOR PPLICATIONS STS-1 Pulse Template Lower Curve Upper Curve -0.2 Time, in UI 11. M IGURE ICROPROCESSOR ERIAL...

  • Page 27: Microprocessor Serial Interface Timing (See Figure 12)

    XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED ICROPROCESSOR ERIAL NTERFACE IMING IGURE YMBOL ARAMETER NITS CS Low to Rising Edge of SClk Setup Time...

  • Page 28: System Description

    • The Transmit Section - Channels 0, 1, 2, and 3 2. The XRT73L04B is configured via input pin set- tings. • The Receive Section - Channels 0, 1, 2, and 3 The XRT73L04B can be configured to operate in the •...

  • Page 29: 1.0 Selecting The Data Rate

    1.0 SELECTING THE DATA RATE 1.1 C ONFIGURING HANNEL Each channel within the XRT73L04B can be config- For the following disscussion the reader should refer ured to support the E3 (34.368 Mbps), DS3 (44.736 toTable 2 to determine the appropriate Address for Mbps) or the SONET STS-1 (51.84 Mbps) rates.
  • Page 30 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 2: H XRT73L04B C ABLE EXADECIMAL DDRESSES AND ORMATS OF OMMAND EGISTERS EGISTER ORMAT COMMAND ADDRESS TYPE REGISTER HANNEL 0x00 CR0-0 RLOL_0 RLOS_0 ALOS_0 DLOS_0 DMO_0 0x01 CR1-0 TxOFF_0 TAOS_0 TxClkINV_0...

  • Page 31: Command Register, Cr4-(N)

    XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 2: H XRT73L04B C ABLE EXADECIMAL DDRESSES AND ORMATS OF OMMAND EGISTERS EGISTER ORMAT COMMAND ADDRESS TYPE REGISTER HANNEL 0x18 CR0-3 RLOL_3 RLOS_3 ALOS_3 DLOS_3 DMO_3 0x19 CR1-3 TxOFF_3 TAOS_3 TxClkINV_3...

  • Page 32: 2.0 The Transmit Section

    LOCK Figure 13 indicates that the Transmit Section within The purpose of the Transmit Logic Block is to accept each Channel of the XRT73L04B consists of the fol- either Dual-Rail or Single-Rail (e.g., a binary data lowing blocks: stream) TTL/CMOS level data and timing information from the Terminal Equipment.

  • Page 33: Accepting Single-Rail Data From The Terminal Equipment

    30% to 70% and converts them The on-chip Pulse-Shaping circuitry within the Trans- to a 50% duty cycle. mit Section of each Channel in the XRT73L04B gen- erates pulses of the appropriate shapes and width to 2.3 T...

  • Page 34: Hdb3 Encoding

    "0’s", with either a "000V" or a "B00V" pattern. The HDB3 Encoder decides whether to substitute with ei- If the XRT73L04B is configured to operate in the E3 ther the "000V" or the "B00V" pattern in order to in- Mode, then the HDB3/B3ZS Encoder blocks operate sure that an odd number of bipolar pulses exist be- in the HDB3 Mode.

  • Page 35: Command Register Cr3-(N)

    LOSMUT_(n) RxOFF RxClk_(n)INV Reserved : This method can only be used if the XRT73L04B is uration of each channel to transmit an output pulse operating in the HOST Mode. which is compliant to either of the following pulse If either of these methods are used to disable the...

  • Page 36: Enabling The Transmit Line Build-Out Circuit

    If the Transmit Line Build-Out circuit is disabled, then a. Operating in the Hardware Mode the XRT73L04B outputs partially shaped pulses onto Set the TxLEV_(n) input pin to “High". the line via the TTIP_(n) and TRing_(n) output pins.

  • Page 37: Command Register, Cr1-(N)

    Transmit Line Build-Out circuit ial cable are to be terminated with 75 Ohm resistor. by setting the TxLEV_(n) input pin or bit-field to Interface the Transmit Section of the XRT73L04B in "1". the manner illustrated in Figure 21.

  • Page 38: Transformer Recommendations

    XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TRANSFORMER RECOMMENDATIONS ARAMETER ALUE Turns Ratio Primary Inductance 40µH Isolation Voltage 1500Vrms Leakage Inductance 0.6µH UMBER ENDOR NSULATION ACKAGE PE-68629 Pulse 3000V Large Thru-Hole PE-65966 Pulse 1500V Small Thru-Hole PE-65967 Pulse...

  • Page 39: 3.0 The Receive Section

    XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 3.0 THE RECEIVE SECTION line and encode it back into the TTL/CMOS format where it can be received and processed by the Termi- Figure 13 indicates the Receive Section consists of nal Equipment.

  • Page 40: The Receive Equalizer Block

    DSX-3 or STSX-1 Pulse Template requirements. For state to set the Receive Equalizer when the overall the XRT73L04B, this is achieved by setting the cable-length, from the local Receiving Terminal to the TXLEV_(n) input pin or bit-field to the appropriate lev- remote Transmitting Terminal is NOT known.

  • Page 41: Command Register

    DSX-3 or the STSX-1 Cross Connect : The results of extensive testing indicates that when the Receive Equalizer is enabled, the XRT73L04B is capa- are required to meet the Isolated Pulse Template ble of receiving an E3 line signal with anywhere from 0 to Requirements per Bellcore GR-499-CORE for 12dB of cable loss over the Industrial Temperature range.

  • Page 42: Clock Recovery Pll

    3.4.1 B3ZS Decoding (DS3/STS-1 Applications) RTIP and RRing input pins, or if the frequency differ- If the XRT73L04B is configured to operate in the DS3 ence between the line signal and that applied via the or STS-1 Modes, then the HDB3/B3ZS Decoding EXClk_(n) input pin exceeds 0.5%, then the channel...

  • Page 43: 3.4.3 Configuring The Hdb3/B3Zs Decoder

    1. The amplitude of the incoming line signal via the In general, the LOS Declaration/Clearance scheme RTIP and RRing inputs. that is employed in the XRT73L04B is based upon 2. The number of pulses detected in the incoming ITU-T Recommendation G.775 for both E3 and DS3 line signal within a certain amount of time.
  • Page 44 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 When the XRT73L04B is operating in the E3 Mode, a receive line signal amplitude rises back to -15dB or given channel declares an LOS Condition if its re- above. Figure 26 illustrates the signal levels at which ceive line signal amplitude drops to -35dB or below.

  • Page 45: Signal

    1. The Analog LOS (ALOS) Declaration/Clearance for DS3 and STS-1 Applications Criteria When the XRT73L04B is operating in the DS3 or A channel declares an Analog LOS (ALOS_(n)) Con- STS-1 Mode, then each channel declares and clears dition if the amplitude of the incoming line signal LOS based upon the following two criteria.

  • Page 46: Command Register Cr0-(N)

    DLOS Monitoring the State of DLOS condition. If the XRT73L04B is operating in the HOST Mode the Disabling the DLOS Detector state of DLOS_(n) of Channel(n) can be polled or For debugging purposes, it is useful to disable the monitored by reading in the contents of Command DLOS_(n) detector.

  • Page 47: Command Register Cr3-( N )

    4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 In some applications it is not desirable for a channel This feature is available whenever XRT73L04B is op- within the E3/DS3/STS-1 LIU to recover data and erating in the HOST Mode or Hardware Mode.
  • Page 48 Setting the RxClkINV pin “High” results in all chan- ty pulse in the incoming line signal via the RTIP_(n) nels of the XRT73L04B to output the recovered data and RRing_(n) input pins, then the channel(n) pulses on RPOS_(n) and RNEG_(n) on the falling edge of its corresponding RNEG_(n) output pin “High".

  • Page 49: Command Register Cr3-(N)

    RPOS_(n) and RxClk_(n) output pins, as illustrat- pulling the (SR/DR) pin to VDD. ed in Figure 31 and Figure 32. : When the XRT73L04B is operating in the Hardware Mode, the setting of the (SR/DR) input pin applies globally b. Operating in the Hardware Mode to all channels.

  • Page 50: Shutting Off The Receive Section

    “High". Turn on the Receiver Sections by The Receive Section of each channel in the pulling the RxOFF input pin to “Low". XRT73L04B can be shut off. This feature may come b. Operating in the HOST Mode in handy in some redundant system designs. Particu- Shut off the Receive Sections by writing a "1"...

  • Page 51: Diagnostic Features Of The Xrt73L04B

    This data is processed through the Transmit Clock Duty Cycle Adjust PLL and the HDB3/B3ZS The XRT73L04B supports equipment diagnostic ac- Encoder. Finally, this data is output to the line via the tivities by supporting the following Loop-Back modes TTIP_(n) and TRing_(n) output pins.

  • Page 52: The Digital Local Loop -Back Mode

    RTIP and RRing in- COMMAND REGISTER CR4-(n) put pins. The Transmitting Terminal Equipment trans- mits clock and data into the XRT73L04B via the TP- Data, TNData and TxClk input pins. This data is pro- STS-1/DS3_(n)

  • Page 53: The Remote Loop -Back Mode

    XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 b. Operating in the Hardware Mode. put to the Receive Terminal Equipment via the RPOS, RNEG and RxClk output pins. Additionally, this data To configure Channel (n) to operate in the Digital Lo-...

  • Page 54: T Xoff Features

    EATURES COMMAND REGISTER CR1-(n) The Transmit Section of each Channel in the XRT73L04B can be shut off. When this feature is in- voked, the Transmit Section of the configured chan- TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) Reserved nel is shut-off and the Transmit Output signals (e.g., TTIP_(n) and TRing_(n)) is tri-stated.

  • Page 55: The Taos (Transmit All One S) Feature

    TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) Reserved signal toggles "High". : The Transmit Drive Monitor circuit does not have to be used to operate the Transmit Section of the XRT73L04B. Terminate the all “1’s" pattern by writing to Command This is purely a diagnostic feature.
  • Page 56 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 7: H XRT73L04B C ABLE EXADECIMAL DDRESSES AND ORMATS OF OMMAND EGISTERS EGISTER ORMAT COMMAND ADDRESS TYPE REGISTER HANNEL 0x00 CR0-0 RLOL_0 RLOS_0 ALOS_0 DLOS_0 DMO_0 0x01 CR1-0 TxOFF_0 TAOS_0 TxClkINV_0...

  • Page 57: Description Of Bit -Fields For Each Command Register

    Channel(n) of the Receiver is currently declaring an type of registers or Read/Write (R/W) type of regis- LOS (Loss of Signal) Condition. ters. Each channel of the XRT73L04B has eight command registers, CR0-(n) through CR7-(n) where This bit-field is set to "0" if Channel(n) is not currently (n) = 0, 1, 2 or 3.

  • Page 58: Command Register Cr1-(N)

    225 feet. bit-field turns on the Transmitter. This bit-field is active only if the XRT73L04B is config- Bit D3 - TAOS_(n) (Transmit All OneS - Chan- ured to operate in the DS3 or SONET STS-1 Modes.

  • Page 59: Command Register Cr3-(N)

    Redundancy System. : This Encoder/Decoder performs HDB3 Encoding/ Decoding if the XRT73L04B is operating in the E3 Mode. Writing a "1" into this bit-field shuts off the Receive Otherwise, it performs B3ZS Encoding/Decoding.

  • Page 60: Command Register Cr4-(N)

    ERIAL Figure 38. NTERFACE The XRT73L04B Serial Interface is a simple four wire In order to use the Microprocessor Serial Interface, a interface that is compatible with many of the micro- clock signal must be first applied to the SClk input controllers available in the market.
  • Page 61 Write operation. The address selects the Command the desired eight bit data word to the SDI input pin via Register in the XRT73L04B that the user is either the Microprocessor Serial Interface. The Micropro- reading data from or writing data to. The address bits...
  • Page 62 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 38. T IGURE IMING IAGRAM FOR THE ICROPROCESSOR ERIAL NTERFACE SCLK SCLK Hi-Z Hi-Z...

  • Page 63: Ordering Information

    XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ORDERING INFORMATION ACKAGE PERATING TEMPERATURE ANGE XRT73L04BIV 144 Pin LQFP 20 x 20 x 1.4mm -40°C to +85°C Theta-J = 24° C/W Theta-J = 5.5° C/W HERMAL NFORMATION PACKAGE DIMENSIONS 144 LEAD QUAD FLAT PACK (20 x 20 x 1.4 mm LQFP)

  • Page 64: Revision History

    EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo- ration is adequately protected under the circumstances.

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