Exar XRT73L06IB-F Manuals

Manuals and User Guides for Exar XRT73L06IB-F. We have 1 Exar XRT73L06IB-F manual available for free PDF download: Manual

Exar XRT73L06IB-F Manual (64 pages)

4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

Brand: Exar | Category: Recording Equipment | Size: 0.8 MB

Table of Contents
4
General Description Features Applications
5
Typical Applications
6
Receive Interface Characteristics
6
Ordering Information
7
Pin Descriptions ( by Function )
8
Transmit Interface
8
Receive Interface
10
Clock Interface
11
Operating Mode Select
12
Control and Alarm Interface
13
Microprocessor Interface
15
Power and Ground Pins
17
No Connection Pins
18
Electrical Characteristics
19
Absolute Maximum Ratings
19
DC Electrical Characteristics
19
AC Electrical Characteristics (See Figure 5)
20
Terminal Side Timing Parameters (See Figure 6 and Figure 7) -- {(N) = 0, 1, 2 or 3
20
Line Side Parameters E3 Application
22
Transmit Characteristics (See Figure 5)
22
Line Side Parameters Sonet STS-1 Application
23
Transmit Characteristics (See Figure 5)
23
Line Side Parameters DS3 Application
24
Transmit Characteristics (See Figure 5)
24
Microprocessor Serial Interface Timing (See Figure 12)
27
System Description
28
The Transmit Section - Channels 0, 1, 2, and 3
28
The Receive Section - Channels 0, 1, 2 and 3
28
The Microprocessor Serial Interface
28
1.0 Selecting the Data Rate
29
Onfiguring Hannel
29
COMMAND REGISTER, CR4-(N)
31
2.0 the Transmit Section
32
The Transmit Logic Block
32
Accepting Dual-Rail Data from the Terminal Equipment
32
Accepting Single-Rail Data from the Terminal Equipment
33
COMMAND REGISTER CR3-(N)
33
The Transmit Clock Duty Cycle Adjust Circuitry
33
The Hdb3/B3Zs Encoder Block
33
2.3.1 B3ZS Encoding
33
HDB3 Encoding
34
2.3.3 Disabling the HDB3/B3ZS Encoder
34
COMMAND REGISTER CR3-(N)
35
The Transmit Pulse Shaping Circuitry
35
He Ransmit Ulse Haping Ircuitry
35
Enabling the Transmit Line Build-Out Circuit
36
COMMAND REGISTER, CR1-(N)
36
Disabling the Transmit Line Build-Out Circuit
36
COMMAND REGISTER, CR1-(N)
37
Design Guideline for Setting the Transmit Line Build-Out Circuit
37
The Transmit Line Build-Out Circuit and E3 Applications
37
Interfacing the Transmit Sections of the Xrt73L04B to the Line
37
Transformer Recommendations
38
3.0 the Receive Section
39
Interfacing the Receive Sections of the Xrt73L04B to the Line
39
The Receive Equalizer Block
40
Guidelines for Setting the Receive Equalizer
40
Channel Ds3/E3/Sts-1 Line Interface Unit Rev
40
Command Register
41
Clock Recovery Pll
42
The Training Mode
42
The Data/Clock Recovery Mode
42
The Hdb3/B3Zs Decoder
42
B3ZS Decoding (DS3/STS-1 Applications)
42
HDB3 Decoding (E3 Applications)
42
3.4.3 Configuring the HDB3/B3ZS Decoder
43
COMMAND REGISTER CR3-(N)
43
Los Declaration /Clearance
43
The LOS Declaration/Clearance Criteria for E3 Applications
43
Signal
45
The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications
45
(DS3 and STS-1 Applications)
45
COMMAND REGISTER CR0-(N)
46
COMMAND REGISTER CR2-(N)
46
Muting the Recovered Data While the LOS Is Being Declared
46
Command Register Cr3-( N )
47
Routing Dual-Rail Format Data to the Receiving Terminal Equipment
47
COMMAND REGISTER CR3-(N)
49
Routing Single-Rail Format (Binary Data Stream) Data to the Receive Terminal Equipment
49
Shutting off the Receive Section
50
COMMAND REGISTER CR3-(N)
50
Diagnostic Features of the Xrt73L04B
51
The Analog Local Loop -Back Mode
51
The Digital Local Loop -Back Mode
52
Command Register Cr4
52
COMMAND REGISTER CR4-(N)
52
The Remote Loop -Back Mode
53
He Emote Oop Ack Ode
53
COMMAND REGISTER CR4-(N)
53
T Xoff Features
54
COMMAND REGISTER CR1-(N)
54
The Transmit Drive Monitor Features
54
The Taos (Transmit All One S) Feature
55
The Microprocessor Serial Interface
55
Escription of the Ommand Egisters
55
COMMAND REGISTER CR1-(N)
55
Description of Bit -Fields for each Command Register
57
COMMAND REGISTER CR0-(N)
57
COMMAND REGISTER CR1-(N)
58
Command Register CR2-(N)
58
Ommand Egister Cr2-( )
58
COMMAND REGISTER CR3-(N)
59
Command Register CR4-(N)
60
Operating the Microprocessor Serial Interface
60
Ordering Information
63
Revision History
64

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