Exar XRT73L03A Manual

3 channel ds3/e3/sts-1 line interface unit

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NOVEMBER 2001

GENERAL DESCRIPTION

The XRT73L03A, 3-Channel, DS3/E3/STS-1 Line In-

terface Unit is an improved version of the XRT73L03

and consists of three independent line transmitters

and receivers integrated on a single chip designed for

DS3, E3 or SONET STS-1 applications.

Each channel of the XRT73L03A can be configured

to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)

or the SONET STS-1 (51.84 Mbps) rates. Each

channel can be configured to operate in a mode/data

rate that is independent of the other channels.

In the transmit direction, each channel encodes input

data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-

mat and converts the data into the appropriate pulse

shapes for transmission over coaxial cable via a 1:1

transformer.

In the receive direction, the XRT73L03A performs

equalization on incoming signals, performs Clock Re-

covery, decodes data from either B3ZS or HDB3 for-

mat, converts the receive data into TTL/CMOS for-

mat, checks for LOS or LOL conditions and detects

and declares the occurrence of Line Code Violations.

1. XRT73L03A B

IGURE

E3_(n)

RTIP_(n)

Equalizer

RRing_(n)

REQEN_(n)

LOSTHR_(n)

SDI

SDO

Processor

SClk

Interface

REGR

TTIP_(n)

TRing_(n)

MTIP_(n)

MRing_(n)

DMO_(n)

Notes: 1. (n) = 0, 1, or 2 for respective Channels

2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.

Exar

Corporation 48720 Kato Road, Fremont CA, 94538

LOCK

IAGRAM

STS-1/DS3_(n)

Host/(HW)

RLOL_(n) EXClk_(n)

AGC/

Slicer

Peak

Detector

LOS Detector

Serial

Loop MUX

HDB3/

Pulse

B3ZS

Shaping

Encoder

Device

Control

Monitor

3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

FEATURES

• Incorporates an improved Timing Recovery circuit

and is pin and functional compatible to XRT73L03

• Meets E3/DS3/STS-1 Jitter Tolerance Require-

ments

• Contains a 4-Wire Microprocessor Serial Interface

• Full Loop-Back Capability

• Transmit and Receive Power Down Modes

• Full Redundancy Support

• Uses Minimum External components

• Single +3.3V Power Supply

• 5V tolerant I/O

• -40°C to +85°C Operating Temperature Range

• Available in a Thermally Enhanced 120 pin TQFP

package

APPLICATIONS

• Digital Cross Connect Systems

• CSU/DSU Equipment

• Routers

• Fiber Optic Terminals

• Multiplexers

• ATM Switches

RxOFF

RxClkINV

Clock

Invert

Recovery

Data

Recovery

Decoder

Transmit

Logic

Duty Cycle Adjust

Channel 0 - (n) = 0

Channel 1 - (n) = 1

Channel 2 - (n) = 2

•

(510) 668-7000

FAX (510) 668-7017

XRT73L03A

RxClk_(n)

RPOS_(n)

HDB3/

B3ZS

RNEG_(n)

LCV_(n)

ENDECDIS

RLOS_(n)

LLB_(n)

RLB_(n)

TAOS_(n)

TPData_(n)

TNData_(n)

TxClk_(n)

TxLEV_(n)

TxOFF_(n)

•

www.exar.com

REV. 2.0.0

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Summary of Contents for Exar XRT73L03A

Page 1 DS3, E3 or SONET STS-1 applications. • Contains a 4-Wire Microprocessor Serial Interface Each channel of the XRT73L03A can be configured • Full Loop-Back Capability to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) • Transmit and Receive Power Down Modes or the SONET STS-1 (51.84 Mbps) rates.
Page 2: Typical Applications
áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 TYPICAL APPLICATIONS 2. M ATM A IGURE ULTI HANNEL PPLICATION RPOS RPOS RPOS RRPOS RTIP RNEG RNEG RNEG RRNEG RRing RxClk RxClk RxLineClk RRClk Switch/ XRT72L73 XRT71D03...
Page 3: General Description
áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 4. P XRT73L03A 120 P TQFP IGURE IN OUT OF THE IN THE PACKAGE EXDGND RLOL_2 LCV_2 EXDVDD EXClk_1 RLOS_2 RLOL_0 REQEN_2 STS1/DS3_2 LCV_0 RLOS_0 E3_2 EXClk_2...
Page 4: Table Of Contents
áç áç áç áç XRT73L03A 3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 TABLE OF CONTENTS GENERAL DESCRIPTION ....................1 ..............................1 EATURES APPLICATIONS ............................1 ..........................2 YPICAL PPLICATIONS : ..................... 2 RANSMIT NTERFACE HARACTERISTICS : ....................... 2 ECEIVE...
Page 5 OMMAND EGISTER 3.7 S ......................47 HUTTING ECEIVE ECTION CR3-( ) ...................... 47 OMMAND EGISTER 4.0 Diagnostic Features of the XRT73L03A ..................48 4.1 T ......................48 NALOG OCAL 4.2 T ......................49 IGITAL OCAL CR4-( ) ...................... 49...
Page 6: Pin Descriptions (By Function)
TxClk_(n). TPData_0 Transmit Positive Data Input - Channel (n) TPData_1 The XRT73L03A samples this pin on the falling edge of TxClk_(n). If the TPData_2 device samples a "1", then it generates and transmits a positive polarity pulse to the line.
Page 7 The XRT73L03A is configured to operate in either the DS3 or SONET STS-1 Modes. The XRT73L03A is configured to operate in the Hardware Mode. : This pin to should be tied to GND if the XRT73L03A is going to be operating in the HOST Mode, (internally pulled-down). TxOFF_0...
Page 8: Receive Interface
Equalizer. The guidelines for enabling and disabling the Receive Equal- izer are described in Section 3.2. : This pin is ignored and should be tied to GND if the XRT73L03A is going to be operating in the HOST Mode, (internally pulled-down).
Page 9: Clock Interface
Register Reset Input pin (Invert RxClk(n)) Output - Select): REGR/ RxClkINV The function of this pin depends upon whether the XRT73L03A is oper- ating in the HOST Mode or in the Hardware Mode. : This pin is internally pulled "High".
Page 10 The XRT73L03A ignores this pin if the E3_(n) pin is set to "1". This input pin is ignored if the XRT73L03A is operating in the HOST Mode. : This pin should be tied to GND if the XRT73L03A is going to be operating in the HOST Mode, (internally pulled-down). HOST/Hardware Mode Select:...
Page 11: Control And Alarm Interface
The frequency of this "1’s" pattern is determined by TxClk_(n). This input pin is ignored if the XRT73L03A is operating in the HOST Mode. : This pin should be tied to GND if the XRT73L03A is going to be operating in the HOST Mode, (internally pulled-down). RLOS_0...
Page 12 A "High" on this pin with RLB_(n) also being set to "High" configures Channel (n) to operate in the Digital Local Loop-Back Mode. : This pin is ignored and should be tied to GND if the XRT73L03A is going to be operating in the HOST Mode.
Page 13: Microprocessor Interface
B3ZS format for STS-1/DS3 operation or in the HDB3 format for E3 oper- ation. : If the XRT73L03A is operating in the Hardware Mode, this pin setting configures the B3ZS/HDB3 Encoder and Decoder Blocks for all Channels.
Page 14 Register Reset Input pin (Invert RxClk(n)) Output - Select): REGR/ RxClkINV The function of this pin depends upon whether the XRT73L03A is oper- ating in the HOST Mode or in the Hardware Mode. : This pin is internally pulled "High".
Page 15: Power And Ground Pins
áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 POWER AND GROUND PINS PIN # NAME TYPE DESCRIPTION TxAVDD_1 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) TxAGND_1 **** Transmitter Analog Ground - Channel(n) TxAGND_2...
Page 16: N O Connection Pins
áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 NO CONNECTION PINS PIN # NAME TYPE DESCRIPTION No connection No connection No connection No connection...
Page 17: Electrical Characteristics
Theta-JA 23° C/W Theta-JC 7° C/W : The XRT73L03A is assembled in a thermally dered to the mounting board if desired, but must be electri- enhanced package with an integral Copper Heat Slug. The cally isolated from any V connections.
Page 18 RxClk_(n) Clock Rise Time (10% to 90%) RxClk_(n) Clock Fall Time (10% to 90%) Input Capacitance Load Capacitance 2. All XRT73L03A digital outputs are also TTL 5V OTES compliant. However, these outputs will not drive to 1. All XRT73L03A digital inputs are designed to be 5V nor will they accept external 5V pull-ups.
Page 19 áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 5. T E3, DS3 STS-1 R IGURE RANSMIT ULSE MPLITUDE IRCUIT FOR ATES TYPICAL CHANNEL TTIP_(n) 31.6 Ω Channel (n) Channel (n) TxPOS_(n) TPData_(n) TxNEG_(n) TNData_(n) 75 Ω...
Page 20 áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED E3 A ARAMETERS PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS...
Page 21 áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED STS-1 A ARAMETERS ONET PPLICATION RANSMIT HARACTERISTICS IGURE YMBO ARAMETER...
Page 22 áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED DS3 A ARAMETERS PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS Transmit Output Pulse Amplitude (Measured at 0 feet, TxLEV=0) 0.65...
Page 23 áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 Figure 8, Figure 9 and Figure 10 present the Pulse Template requirements for the E3, DS3 and STS-1 Rates. 8. ITU-T G.703 T E3 A IGURE RANSMIT...
Page 24 áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 10. B GR-253-CORE T SONET STS-1 A IGURE ELLCORE RANSMIT UTPUT ULSE EMPLATE FOR PPLICATIONS STS-1 Pulse Template Lower Curve Upper Curve -0.2 Time, in UI 11. M...
Page 25 áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED ICROPROCESSOR ERIAL NTERFACE IMING IGURE YMBOL ARAMETER NITS CS Low to Rising Edge of SClk Setup Time...
Page 26: System Description
1. The Microprocessor Serial Interface block is dis- abled. A functional block diagram of the XRT73L03A E3/ 2. The XRT73L03A is configured via input pin set- DS3/STS-1 Transceiver IC is presented in Figure 13. tings. The XRT73L03A contains three separate channels...
Page 27: Selecting The Data Rate
1.0 SELECTING THE DATA RATE 1.1 C ONFIGURING HANNEL Each channel within the XRT73L03A can be config- For the following disscussion the reader should refer ured to support the E3 (34.368 Mbps), DS3 (44.736 toTable 2 to determine the appropriate Address for Mbps) or the SONET STS-1 (51.84 Mbps) rates.
Page 28 áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 2: H XRT73L03A C ABLE EXADECIMAL DDRESSES AND ORMATS OF OMMAND EGISTERS EGISTER ORMAT COMMAND ADDRESS TYPE REGISTER HANNEL 0x00 CR0-0 RLOL_0 RLOS_0 ALOS_0 DLOS_0 DMO_0 0x01...
Page 29: The Transmit Section
• TxClk_(n) Figure 13 indicates that the Transmit Section within Figure 14 illustrates the typical interface for the trans- each Channel of the XRT73L03A consists of the fol- mission of data in a Dual-Rail Format between the lowing blocks: Terminal Equipment and the Transmit Section of the XRT73L03A.
Page 30: Accepting Single-Rail Data From The Terminal Equipment
TTIP_(n) and TRing_(n) To transmit data in a Single-Rail data from the Termi- output pins. nal Equipment, configure the XRT73L03A in the HOST Mode. OTES 1. In this mode, the Transmit Logic Block ignores the Write a "1"...
Page 31: The Transmit Clock Duty Cycle Adjust Circuitry
CUITRY The on-chip Pulse-Shaping circuitry within the Trans- 2.3.1 B3ZS Encoding mit Section of each Channel in the XRT73L03A gen- If the XRT73L03A has been configured to operate in erates pulses of the appropriate shapes and width to the DS3 or SONET STS-1 Modes, then the HDB3/ meet the applicable pulse template requirements.
Page 32: Hdb3 Encoding
HDB3 Encoder decides whether to substitute with ei- ther the "000V" or the "B00V" pattern in order to in- If the XRT73L03A is configured to operate in the E3 sure that an odd number of bipolar pulses exist be- Mode, then the HDB3/B3ZS Encoder blocks operate tween any two consecutive violation pulses.
Page 33: The Transmit Pulse Shaping Circuitry
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 COMMAND REGISTER CR2-(n) : This method can only be used if the XRT73L03A is uration of each channel to transmit an output pulse operating in the HOST Mode. which is compliant to either of the following pulse...
Page 34: Enabling The Transmit Line Build-Out Circuit
If the Transmit Line Build-Out circuit is disabled, then a. Operating in the Hardware Mode the XRT73L03A outputs partially shaped pulses onto Set the TxLEV_(n) input pin to “High". the line via the TTIP_(n) and TRing_(n) output pins.
Page 35: Command Register, Cr1-(N)
75 Ohm resistor. feet, disable the Transmit Line Build-Out circuit by Interface the Transmit Section of the XRT73L03A in setting the TxLEV_(n) input pin or bit-field to "1". the manner illustrated in Figure 21.
Page 36: Transformer Recommendations
áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 TRANSFORMER RECOMMENDATIONS ARAMETER ALUE Turns Ratio Primary Inductance 40µH Isolation Voltage 1500Vrms Leakage Inductance 0.6µH UMBER ENDOR NSULATION ACKAGE PE-68629 Pulse 3000V Large Thru-Hole PE-65966 Pulse 1500V...
Page 37: The Receive Section
áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 3.0 THE RECEIVE SECTION where it can be received and processed by the Termi- nal Equipment. Figure 13 indicates the Receive Section consists of the following blocks: 3.1 I...
Page 38: The Receive Equalizer Block
áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 Figure 23 presents the recommended schematic for capacitive-coupling each Receive Section of the XRT73L03A to the line. 23. R IGURE ECOMMENDED CHEMATIC FOR NTERFACING THE ECEIVE ECTION OF THE...
Page 39: Guidelines For Setting The Receive Equalizer
DSX-3 or STSX-1 Pulse Template requirements. For 3.2.1.1 If the Overall Cable Length is NOT the XRT73L03A device, this is achieved by setting the Known TXLEV_(n) input pin or bit-field to the appropriate lev- This section presents recommendations on what...
Page 40: Command Register Cr2-(N)
Requirements per Bellcore GR-499-CORE for : The results of extensive testing indicates that when the Receive Equalizer is enabled, the XRT73L03A device is DS3 applications, or Bellcore GR-253-CORE for capable of receiving an E3 line signal with anywhere from 0 STS-1 applications.
Page 41: The Training Mode
EXClk_(n) input pin exceeds 0.5%, then the channel If the XRT73L03A is configured to operate in the DS3 operates in the Training Mode. When the channel is or STS-1 Modes, then the HDB3/B3ZS Decoding operating in the Training Mode, it does the following: Blocks performs B3ZS Decoding.
Page 42: Configuring The Hdb3/B3Zs Decoder
DLOSDIS_(n) REQEN_(n) b. Operating in the Hardware Mode If a given channel of the XRT73L03A determines that the incoming line signal is missing due to either insuf- To globally enable all HDB3/B3ZS Decoder blocks in ficient amplitude or a lack of pulses in the incoming the XRT73L03A, pull the ENDECDIS input pin “Low".
Page 43: The Los Declaration/Clearance Criteria For E3 Applications
-15dB or above. Figure 27 illustrates the signal levels at which When the XRT73L03A is operating in the E3 Mode, a each channel of the XRT73L03A declares and clears given channel declares an LOS Condition if its re- LOS.
Page 44: The Los Declaration/Clearance Criteria For Ds3 And Sts-1 Applications
1. The Analog LOS (ALOS) Declaration/Clearance for DS3 and STS-1 Applications Criteria When the XRT73L03A is operating in the DS3 or A channel declares an Analog LOS (ALOS_(n)) Con- STS-1 Mode, then each channel declares and clears dition if the amplitude of the incoming line signal LOS based upon the following two criteria.
Page 45: Command Register Cr0-(N)
“0”, then the channel(n) is currently declaring Monitoring the State of DLOS the DLOS condition. If the XRT73L03A is operating in the HOST Mode the Disabling the DLOS Detector state of DLOS_(n) of Channel(n) can be polled or...
Page 46: Command Register Cr3-( N )
Muting upon LOS feature globally for all channels. nal. b. Operating in the HOST Mode. This feature is available whenever XRT73L03A is op- The Muting upon LOS feature for each Channel can erating in the HOST Mode or Hardware Mode.
Page 47 Setting the RxClkINV pin “High” results in all chan- ty pulse in the incoming line signal via the RTIP_(n) nels of the XRT73L03A to output the recovered data and RRing_(n) input pins, then the channel(n) pulses on RPOS_(n) and RNEG_(n) on the falling edge of its corresponding RNEG_(n) output pin “High".
Page 48: Command Register Cr3-(N)
RPOS_(n) and RxClk_(n) output pins, as illustrat- pulling the (SR/DR) pin to VDD. ed in Figure 32 and Figure 33. : When the XRT73L03A is operating in the Hardware Mode, the setting of the (SR/DR) input pin applies globally b. Operating in the Hardware Mode to all channels.
Page 49: Shutting Off The Receive Section
“High". Turn on the Receiver Sections by The Receive Section of each channel in the pulling the RxOFF input pin to “Low". XRT73L03A can be shut off. This feature may come b. Operating in the HOST Mode in handy in some redundant system designs. Particu- Shut off the Receive Sections by writing a "1"...
Page 50: Diagnostic Features Of The Xrt73L03A
This data is processed through the Transmit Clock Duty Cycle Adjust PLL and the HDB3/B3ZS The XRT73L03A supports equipment diagnostic ac- Encoder. Finally, this data is output to the line via the tivities by supporting the following Loop-Back modes TTIP_(n) and TRing_(n) output pins.
Page 51: He Igital Ocal Oop Ack Ode
RTIP and RRing input COMMAND REGISTER CR4-(n) pins. The Transmitting Terminal Equipment transmits clock and data into the XRT73L03A via the TPData, TNData and TxClk input pins. This data is processed STS-1/DS3_(n) E3_(n)
Page 52: The Remote Loop -Back Mode
áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 To configure Channel (n) to operate in the Digital Lo- put to the Receive Terminal Equipment via the RPOS, cal Loop-Back Mode, pull both the LLB input pin and RNEG and RxClk output pins.
Page 53: T Xoff Features
EATURES COMMAND REGISTER CR1-(n) The Transmit Section of each Channel in the XRT73L03A can be shut off. When this feature is in- voked, the Transmit Section of the configured channel TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n) is shut-off and the Transmit Output signals (e.g., TTIP_(n) and TRing_(n)) is tri-stated.
Page 54: The Taos (Transmit All One S) Feature
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n) Output) signal toggles "High". : The Transmit Drive Monitor circuit does not have to be used to operate the Transmit Section of the XRT73L03A. Terminate the all “1’s" pattern by writing to Command This is purely a diagnostic feature.
Page 55 The Command Registers are either Read-Only (RO) type of registers or Read/Write (R/W) type of regis- The register addresses are presented in the Hexa- ters. Each channel of the XRT73L03A has eight decimal format. command registers, CR0-(n) through CR7-(n) where...
Page 56: Description Of Bit -Fields For Each Command Register
áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 (n) = 0, 1 or 2. The associated addresses for each This Read-Only bit-field indicates whether or not the channel are presented in , (repeated as Table 7).
Page 57: Command Register Cr2-(N)
This Read/Write bit-field is used to enable or disable nel(n) is less than 225 feet. the Channel(n) Transmit Line Build-Out circuit. This bit-field is active only if the XRT73L03A is config- Setting this bit-field "High" disables the Channel(n) ured to operate in the DS3 or SONET STS-1 Modes.
Page 58 Encoder and Decoder blocks. Writing a "0" to this bit- field disables the B3ZS/HDB3 Encoder and Decoder blocks. COMMAND REGISTER CR4-(n) : This Encoder/Decoder performs HDB3 Encoding/ Decoding if the XRT73L03A is operating in the E3 Mode. Otherwise, it performs B3ZS Encoding/Decoding. Reserved STS-1/DS3_(n) E3_(n) LLB_(n) RLB_(n) .Writing a "1"...
Page 59: Operating The Microprocessor Serial Interface
ERIAL (labeled A0, A1, A2 , A3 and A4) NTERFACE The XRT73L03A Serial Interface is a simple four wire The next five rising edges of the SClk signal clocks in interface that is compatible with many of the micro- the 5-bit address value for this particular Read or controllers available in the market.
Page 60 áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 the desired eight bit data word to the SDI input pin via from and/or writing data to this combined signal. This the Microprocessor Serial Interface. The Micropro-...
Page 61: Ordering Information
áç áç áç áç XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.0 ORDERING INFORMATION ACKAGE PERATING TEMPERATURE ANGE XRT73L03AIV 120 Pin Thermally Enhanced TQFP 14mm X 20mm C to +85 Theta-J = 23° C/W Theta-J =7° C/W HERMAL NFORMATION...
Page 62: Revision History
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo- ration is adequately protected under the circumstances.

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