Exar XRT73L04 Manual

4 channel ds3/e3/sts-1 line interface unit

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OCTOBER 2003

GENERAL DESCRIPTION

The XRT73L04A, 4-Channel, DS3/E3/STS-1 Line In-

terface Unit is an improved version of the XRT73L04

and consists of four independent line transmitters and

receivers integrated on a single chip designed for

DS3, E3 or SONET STS-1 applications.

Each channel of the XRT73L04A can be configured

to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)

or the SONET STS-1 (51.84 Mbps) rates. Each

channel can be configured to operate in a mode/data

rate that is independent of the other channels.

In the transmit direction, each channel encodes input

data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-

mat and converts the data into the appropriate pulse

shapes for transmission over coaxial cable via a 1:1

transformer.

In the receive direction, the XRT73L04A performs

equalization on incoming signals, performs Clock Re-

covery, decodes data from either B3ZS or HDB3 for-

mat, converts the receive data into TTL/CMOS for-

mat, checks for LOS or LOL conditions and detects

and declares the occurrence of Line Code Violations.

1. XRT73L04A B

IGURE

E3_(n)

RTIP_(n)

Equalizer

RRing_(n)

REQEN_(n)

LOSTHR

SDI

SDO

Processor

SClk

CS/(SR/DR)

REGR

TTIP_(n)

TRing_(n)

MTIP_(n)

MRing_(n)

DMO_(n)

Notes: 1. (n) = 0, 1, 2 , or 3 for respective Channels

2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in

Hardware Mode.

Exar

Corporation 48720 Kato Road, Fremont CA, 94538

LOCK

IAGRAM

STS-1/DS3_(n)

Host/(HW)

RLOL_(n) EXClk_(n)

AGC/

Slicer

Peak

Detector

LOS Detector

Serial

Loop MUX

Interface

HDB3/

Pulse

B3ZS

Shaping

Encoder

Device

Control

Monitor

4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

FEATURES

• Incorporates an improved Timing Recovery circuit

and is pin and functional compatible to XRT73L04

• Meets E3/DS3/STS-1 Jitter Tolerance Require-

ments

• Contains a 4-Wire Microprocessor Serial Interface

• Full Loop-Back Capability

• Transmit and Receive Power Down Modes

• Full Redundancy Support

• Uses Minimum External components

• Single +3.3V Power Supply

• 5V tolerant I/O

• -40°C to +85°C Operating Temperature Range

• Available in a Thermally Enhanced 144 pin TQFP

package

APPLICATIONS

• Digital Cross Connect Systems

• CSU/DSU Equipment

• Routers

• Fiber Optic Terminals

• Multiplexers

• ATM Switches

RxOFF

RxClkINV

Clock

Invert

Recovery

Data

HDB3/

Recovery

B3ZS

Decoder

Transmit

Logic

Duty Cycle Adjust

Channel 0

Channel 1

Channel 2

Channel 3

•

(510) 668-7000

FAX (510) 668-7017

XRT73L04A

REV. 2.0.3

RxClk_(n)

RPOS_(n)

RNEG_(n)/

(LCV_(n))

RLOS_(n)

LLB_(n)

RLB_(n)

TAOS_(n)

TPData_(n)

TNData_(n)

TxClk_(n)

TxLEV_(n)

TxOFF

•

www.exar.com

Table of Contents

Summary of Contents for Exar XRT73L04

Page 1 • Incorporates an improved Timing Recovery circuit The XRT73L04A, 4-Channel, DS3/E3/STS-1 Line In- and is pin and functional compatible to XRT73L04 terface Unit is an improved version of the XRT73L04 and consists of four independent line transmitters and • Meets E3/DS3/STS-1 Jitter Tolerance Require-...
Page 2 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 TYPICAL APPLICATIONS 2. M ATM A IGURE ULTI HANNEL PPLICATION RPOS RPOS RPOS RRPOS RTIP RNEG RNEG RNEG RRNEG RRing RxClk RxClk RxLineClk RRClk Sw itch/ XRT72L74 XRT71D04 XRT73L04A MClk TPOS TPO S TTIP TNEG...
Page 3 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 4. P XRT73L04A 144 P TQFP IGURE IN OUT OF THE IN THE PACKAGE AGND_2 SDO/E3_0 REGR/(RxClkINV) SDI/E3_1 LOSMUTEN SClk/(RxOFF) AGND_3 CS/(SR/DR) RLOL_3 RLOL_1 RLOS_3 RLOS_1 EXClk_2 EXClk_0 RLOL_2 RLOL_0 RLOS_2 RLOS_0 RxDGND_2 AGND_1...
Page 4: Table Of Contents
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 TABLE OF CONTENTS ......................1 ENERAL DESCRIPTION ..............................1 EATURES APPLICATIONS ............................1 Figure 1.XRT73L04A Block Diagram ........................ 1 ..........................2 YPICAL PPLICATIONS Figure 2.MultiChannel ATM Application ......................2 Figure 3.MultiService - Frame Relay Application ....................2 : .....................
Page 5: General Description Features Applications
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 1.0 SELECTING THE DATA RATE ....................... 25 1.1 C ) ......................25 ONFIGURING HANNEL Table 2:Hexadecimal Addresses and Bit Formats of XRT73L04A Command Registers ....... 26 Table 3:Selecting the Data Rate for Channel(n) via the E3_(n) and STS-1/DS3_(n) input pins (Hardware Mode) , CR4-( ) ......................
Page 6: Typical Applications
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 Figure 24.The Typical Application for the System Installer ................37 Guidelines for Setting the Receive Equalizer ..................37 CR-2( ) ......................38 OMMAND EGISTER 3.3 C PLL ........................39 LOCK ECOVERY The Training Mode ..........................
Page 7: Ordering Information
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 Figure 34. A channel operating in the Analog Local Loop-Back Mode ............48 4.2 T ..................49 IGITAL OCAL CR4-( ) ......................49 OMMAND EGISTER Figure 35.The Digital Local Loop-Back path within a given channel .............. 49 CR4-( ) ......................
Page 8: Pin Descriptions ( By Function )
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 PIN DESCRIPTIONS (BY FUNCTION) TRANSMIT INTERFACE ESCRIPTION TTIP_0 Transmit TTIP Output - Channel (n): TTIP_1 The XRT73L04A uses this pin along with TRing_(n) to transmit a bipolar TTIP_2 line signal via a 1:1 transformer. TTIP_3 TRing_0 Transmit Ring Output - Channel (n):...
Page 9 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 TRANSMIT INTERFACE ESCRIPTION TxLEV_0 Transmit Line Build-Out Enable/Disable Select - Channel (n): TxLEV_1 This input pin permits the Transmit Line Build-Out circuit, within Channel TxLEV_2 (n), to be enabled or disabled. In E3 mode, this pin has no effect on the TxLEV_3 transmit pulse shape.
Page 10: Receive Interface
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 RECEIVE INTERFACE ESCRIPTION RxClk_0 Receive Clock Output - Channel (n): RxClk_1 This output pin is the Recovered Clock signal from the incoming line sig- RxClk_2 nal for Channel (n). The Receive Section of Channel (n) outputs data via RxClk_3 the RPOS_(n) and RNEG_(n) output pins on the rising edge of this clock signal.
Page 11: Clock Interface
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 RECEIVE INTERFACE ESCRIPTION RTIP_0 Receive TIP Input - Channel (n): RTIP_1 This input pin along with RRing_(n) is used to receive the bipolar line sig- RTIP_2 nal from the Remote DS3/E3/STS-1 Terminal. RTIP_3 REQEN_0 Receive Equalization Enable Input - Channel (n):...
Page 12: Operating Mode Select
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 OPERATING MODE SELECT ESCRIPTION Microprocessor Serial Interface - Chip Select Input/Encoder- SR/DR/CS Decoder Disable Input: The function of this pin depends upon whether the XRT73L04A is oper- ating in the HOST Mode or in the Hardware Mode. : This pin is internally pulled "High".
Page 13: Control And Alarm Interface
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 OPERATING MODE SELECT ESCRIPTION HOST/(HW) HOST-Hardware Mode Select: This input pin is used to enable or disable the Microprocessor Serial Interface (e.g., consisting of the SDI, SDO, SClk, and CS pins). Setting this input pin "High"...
Page 14 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 CONTROL AND ALARM INTERFACE ESCRIPTION RNEG_0/(LCV_0) Line Code Violation - Channel (n): RNEG_1/(LCV_1) The function of this pin is dependent on whether the XRT73L04A is in RNEG_2/(LCV_2) the Hardware or HOST Mode (HOST/HW) and if CS/(SR/DR) is set RNEG_3/(LCV_3) “High”.
Page 15: Microprocessor Interface
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 CONTROL AND ALARM INTERFACE ESCRIPTION LOSMUTEN MUTE-upon-LOS Enable Input (Hardware Mode): This input pin is use to configure the XRT73L04A, while it is operating in the Hardware Mode, to MUTE the recovered data via the RPOS_(n), RNEG_(n) output pins whenever one of the Channels declares an LOS conditions.
Page 16 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 MICROPROCESSOR INTERFACE PIN # NAME TYPE DESCRIPTION SDO/E3_0 Serial Data Output from the Microprocessor Serial Interface The function of this pin depends upon the mode of operation. HOST Mode Operation: This pin serially outputs the contents of the specified Command Register during Read Operations.
Page 17: Power And Ground Pins
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 POWER AND GROUND PINS PIN # NAME TYPE DESCRIPTION TxAVDD_2 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) TxAGND_2 **** Transmitter Analog Ground - Channel(n) TxAVDD_3 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) TxAVDD_3 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n)
Page 18: No Connection Pins
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 POWER AND GROUND PINS PIN # NAME TYPE DESCRIPTION RxDGND_3 **** Receiver Digital Ground - Channel(n) RxDVDD_3 **** Receiver Digital Supply 3.3V + 5% - Channel (n) EXDGNDA **** External Clock Digital Ground EXDVDDA **** External Clock Digital Supply...
Page 19: Electrical Characteristics
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Storage Temperature - 65°C to + 150°C Operating Temperature - 40°C to + 85°C Supply Voltage Range -0.5V to +3.465V Theta-JA 20° C/W Theta-JC 6° C/W : The XRT73L04A is assembled in a thermally Ground connections of the device.
Page 20: Ac Electrical Characteristics (See Figure 5)
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 ) (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED AC E LECTRICAL HARACTERISTICS IGURE 7) -- {(n) = 0, 1, 2 ERMINAL IMING ARAMETERS IGURE IGURE...
Page 21 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 5. T E3, DS3 STS-1 R IGURE RANSMIT ULSE MPLITUDE IRCUIT FOR ATES TYPICAL CHANNEL TTIP_(n) 31.6Ω Channel (n) Channel (n) TxPOS_(n) TPData_(n) TxNEG_(n) TNData_(n) 75Ω TxLineClk_(n) TxClk_(n) 31.6Ω TRing_(n) Only One Channel Shown 6.
Page 22: Line Side Parameters E3 Application
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED E3 A ARAMETERS PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS Transmit Output Pulse Amplitude (Measured at Secondary Output of Transformer) Transmit Output Pulse Amplitude Ratio 0.95...
Page 23: Line Side Parameters Sonet Sts-1 Application
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED STS-1 A ARAMETERS ONET PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS Transmit Output Pulse Amplitude (Measured with TxLEV=0) 0.65 0.75 0.90...
Page 24: Line Side Parameters Ds3 Application
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED DS3 A ARAMETERS PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS Transmit Output Pulse Amplitude (Measured at 0 feet, TxLEV=0) 0.65 0.75 0.85...
Page 25 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 Figure 8, Figure 9 and Figure 10 present the Pulse Template requirements for the E3, DS3 and STS-1 Rates. 8. ITU-T G.703 T E3 A IGURE RANSMIT UTPUT ULSE EMPLATE FOR PPLICATIONS 17 ns (14.55 + 2.45)
Page 26 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 10. B GR-253-CORE T SONET STS-1 A IGURE ELLCORE RANSMIT UTPUT ULSE EMPLATE FOR PPLICATIONS STS-1 Pulse Template Lower Curve Upper Curve -0.2 Time, in UI 11. M IGURE ICROPROCESSOR ERIAL NTERFACE TRUCTURE SClk...
Page 27: Microprocessor Serial Interface Timing (See Figure 12)
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED ICROPROCESSOR ERIAL NTERFACE IMING IGURE YMBOL ARAMETER NITS CS Low to Rising Edge of SClk Setup Time CS High to Rising Edge of SClk Hold Time SDI to Rising Edge of SClk Setup Time SDI to Rising Edge of SClk Hold Time...
Page 28: System Description
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 SYSTEM DESCRIPTION a. Operating in the Hardware Mode A functional block diagram of the XRT73L04A E3/ When the XRT73L04A is operating in the Hardware DS3/STS-1 Transceiver IC is presented in Figure 13. Mode, then the following is true: The XRT73L04A contains four separate channels 1.
Page 29: 1.0 Selecting The Data Rate
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 In HOST Mode Operation, the TxOFF input pins can redundancy to quickly switch out a defective line card be used to turn on or turn off the Transmit Output and switch-in the back-up line card. Drivers within all Channels concurrently.
Page 30 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 2: H XRT73L04A C ABLE EXADECIMAL DDRESSES AND ORMATS OF OMMAND EGISTERS EGISTER ORMAT COMMAND ADDRESS TYPE REGISTER HANNEL 0x00 CR0-0 RLOL_0 RLOS_0 ALOS_0 DLOS_0 DMO_0 0x01 CR1-0 TxOFF_0 TAOS_0 TxClkINV_0 TxLEV_0 Reserved 0x02...
Page 31: Command Register, Cr4-(N)
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 2: H XRT73L04A C ABLE EXADECIMAL DDRESSES AND ORMATS OF OMMAND EGISTERS EGISTER ORMAT COMMAND ADDRESS TYPE REGISTER HANNEL 0x18 CR0-3 RLOL_3 RLOS_3 ALOS_3 DLOS_3 DMO_3 0x19 CR1-3 TxOFF_3 TAOS_3 TxClkINV_3 TxLEV_3 Reserved 0x1A...
Page 32: 2.0 The Transmit Section
(E3/DS3 or STS-1 TxLineClk TxClk Framer) Exar E3/DS3/STS-1 LIU The manner that the LIU handles Dual-Rail data is data on the TPData_(n) and TNData_(n) input pins described below and illustrated in Figure 15. The on the falling edge of TxClk_(n).
Page 33: Accepting Single-Rail Data From The Terminal Equipment
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 15. T XRT73L04A S IGURE AMPLES THE DATA ON THE ATA AND ATA INPUT PINS Data TPData TNData TxClk TxClk_(n) is the clock signal that is of the selected data rate frequency, E3 = 34.368 MHz, DS3 = 44.736 COMMAND REGISTER CR3-(n) MHz and STS-1 = 51.84 MHz.
Page 34: The Hdb3/B3Zs Encoder Block
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 meet the applicable pulse template requirements. If the XRT73L04A has been configured to operate in The widths of these output pulses are defined by the the DS3 or SONET STS-1 Modes, then the HDB3/ width of the half-period pulses within the TxClk_(n) B3ZS Encoder blocks operate in the B3ZS Mode.
Page 35: 2.3.3 Disabling The Hdb3/B3Zs Encoder
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 18. A HDB3 E IGURE XAMPLE OF NCODING TClk TPOS SR data Encoded PDATA Encoded NDATA Line signal 2.3.3 Disabling the HDB3/B3ZS Encoder : By executing this step the HDB3/B3ZS Encoder and Decoder blocks in all channels of the XRT73L04A are glo- The XRT73L04A HDB3/B3ZS Encoder can be dis- bally disabled.
Page 36 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 19. T GR-499-CORE T DS3 A IGURE ELLCORE RANSMIT UTPUT ULSE EMPLATE FOR PPLICATIONS D S3 Pu lse T em p late Lower Curve Upper Curve -0.2 Tim e , in UI...
Page 37: Enabling The Transmit Line Build-Out Circuit
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 20. T GR-253-CORE T SONET STS-1 A IGURE ELLCORE RANSMIT UTPUT ULSE EMPLATE FOR PPLI CATIONS ST S-1 Pulse T emplate Lower Curve Upper Curve -0.2 Time, in UI 2.4.1 Enabling the Transmit Line Build-Out Cir- Enable the Transmit Line Build-Out circuit for each cuit channel by doing the following:...
Page 38: Command Register, Cr1-(N)
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 COMMAND REGISTER, CR1-(n) TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) Reserved 2.4.3 Design Guideline for Setting the Transmit over long cable lengths (e.g., greater than 225 feet) cause these pulses to be properly shaped and comply with the Line Build-Out Circuit appropriate pulse template requirement.
Page 39: Transformer Recommendations
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 TRANSFORMER RECOMMENDATIONS ARAMETER ALUE Turns Ratio Primary Inductance 40µH Isolation Voltage 1500Vrms Leakage Inductance 0.6µH UMBER ENDOR NSULATION ACKAGE PE-68629 Pulse 3000V Large Thru-Hole PE-65966 Pulse 1500V Small Thru-Hole PE-65967 Pulse 1500V Small SMT T3001...
Page 40: 3.0 The Receive Section
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 3.0 THE RECEIVE SECTION where it can be received and processed by the Termi- nal Equipment. Figure 13 indicates the Receive Section consists of the following blocks: 3.1 I NTERFACING THE ECEIVE ECTIONS OF THE XRT73L04A...
Page 41: Guidelines For Setting The Receive Equalizer
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 3.2 T Equalizer attempts to restore the shape of the line ECEIVE QUALIZER LOCK signal so that the transmitted data and clock can be The purpose of this block is to equalize the incoming recovered reliably.
Page 42: Command Register
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 When the System Manufacturer is interfacing the Re- In E3 System installation, it is recommended that the ceive Section of the XRT73L04A to the Cross-Con- Receive Equalizer of the XRT73L04A be enabled by nect, they should be aware of the following facts: pulling the REQEN_(n) input pins “High”...
Page 43: Clock Recovery Pll
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 3.3 C 3.4 T HDB3/B3ZS D LOCK ECOVERY ECODER The purpose of the Clock Recovery PLL is to track The Remote Transmitting Terminal typically encodes the incoming Dual-Rail data stream and to derive and the line signal into some sort of Zero Suppression generate a recovered clock signal.
Page 44: 3.4.3 Configuring The Hdb3/B3Zs Decoder
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 Decoder detects this particular pattern, then it substi- Figure 26 illustrates the HDB3 Decoder at work with tutes these bits with a “0000" pattern. two separate Zero Suppression patterns, in the in- coming Dual-Rail Data Stream.
Page 45 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 When the XRT73L04A is operating in the E3 Mode, a receive line signal amplitude rises back to -15dB or given channel declares an LOS Condition if its re- above. Figure 27 illustrates the signal levels at which ceive line signal amplitude drops to -35dB or below.
Page 46: Signal
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 28. T LOS O IGURE EHAVIOR OF THE UTPUT NDICATOR IN RESPONSE TO THE OSS OF IGNAL AND THE TORATION OF IGNAL Actual Occurrence Line Signal of LOS Condition is Restored RTIP/ RRing Time Range for...
Page 47: Command Register Cr0-(N)
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 clearing ALOS_(n) in order to prevent chattering in If the XRT73L04A is operating in the HOST Mode, the RLOS_(n) output signal. the state of ALOS_(n) of Channel(n) can be polled or monitored by reading in the contents of Command Monitoring the State of ALOS_(n) Register CR0.
Page 48: Command Register Cr3-( N )
(E3/DS3 or STS-1 RxClk RxClk Framer) Exar E3/DS3/STS-1 LIU The manner that a given channel transmits Dual-Rail scribed below and illustrated in Figure 30. Each data to the Receiving Terminal Equipment is de- channel(n) typically updates the data on the...
Page 49 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 RPOS_(n) and RNEG_(n) output pins on the rising edge of RxClk_(n). 30. H XRT73L04A RPOS RNEG IGURE OW THE OUTPUTS DATA ON THE OUTPUT PINS RPOS RNEG RxClk RxClk_(n) is the Recovered Clock signal from the in- RNEG_(n) output data to the Receiving Terminal coming Received line signal.
Page 50: Command Register Cr3-(N)
HE TYPICAL INTERFACE FOR THE RANSMISSION OF ATA IN A INGLE ORMAT XRT73L04A FROM THE ECEIVE ECTION OF THE TO THE ECEIVING ERMINAL QUIPMENT RxPOS RPOS Receive Terminal Equipment Logic (E3/DS3 or STS-1 Block RxClk RxClk Framer) Exar E3/DS3/STS-1 LIU...
Page 51: Shutting Off The Receive Section
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 33. T RPOS XRT73L04A IGURE HE BEHAVIOR OF THE LK OUTPUT SIGNALS WHILE THE IS TRANSMIT TING INGLE AIL DATA TO THE ECEIVING ERMINAL QUIPMENT RPOS RxClk : The RNEG_(n) output pin is internally tied to Ground a.
Page 52: Diagnostic Features Of The Xrt73L04A
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 4.0 DIAGNOSTIC FEATURES OF THE via the TPData_(n), TNData_(n) and TxClk_(n) input XRT73L04A pins. This data is processed through the Transmit Clock Duty Cycle Adjust PLL and the HDB3/B3ZS The XRT73L04A supports equipment diagnostic ac- Encoder.
Page 53: The Digital Local Loop -Back Mode
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 any signals that are input to the RTIP and RRing input COMMAND REGISTER CR4-(n) pins. The Transmitting Terminal Equipment transmits clock and data into the XRT73L04A via the TPData, TNData and TxClk input pins. This data is processed STS-1/DS3_(n) E3_(n) LLB_(n)
Page 54: He Emote Oop Ack Ode
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 To configure Channel (n) to operate in the Digital Lo- put to the Receive Terminal Equipment via the RPOS, cal Loop-Back Mode, pull both the LLB input pin and RNEG and RxClk output pins. Additionally, this data the RLB input pin "High".
Page 55: T Xoff Features
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 4.4 T OFF F EATURES COMMAND REGISTER CR1-(n) The Transmit Section of each Channel in the XRT73L04A can be shut off. When this feature is in- voked, the Transmit Section of the configured channel TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) Reserved is shut-off and the Transmit Output signals (e.g., TTIP_(n) and TRing_(n)) is tri-stated.
Page 56: The Taos (Transmit All One S) Feature
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 37. T XRT73L04A IGURE EMPLOYING THE RANSMIT RIVE ONITOR EATURES TTIP_(n) R1 = 31.6Ω TRing_(n) R2 = 31.6Ω TxPOS_(n) TPData_(n) TxNEG_(n) TNData_(n) TxLineClk_(n) TxClk_(n) MTIP_(n) R3 = 270Ω MRing_(n) R4 = 270Ω Channel (n) Only One Channel Shown When the Transmit Drive Monitor circuitry within a...
Page 57 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 7: H XRT73L04A C ABLE EXADECIMAL DDRESSES AND ORMATS OF OMMAND EGISTERS EGISTER ORMAT COMMAND ADDRESS TYPE REGISTER HANNEL 0x00 CR0-0 RLOL_0 RLOS_0 ALOS_0 DLOS_0 DMO_0 0x01 CR1-0 TxOFF_0 TAOS_0 TxClkINV_0 TxLEV_0 Reserved 0x02...
Page 58: Description Of Bit -Fields For Each Command Register
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 7: H XRT73L04A C ABLE EXADECIMAL DDRESSES AND ORMATS OF OMMAND EGISTERS EGISTER ORMAT COMMAND ADDRESS TYPE REGISTER HANNEL 0x18 CR0-3 RLOL_3 RLOS_3 ALOS_3 DLOS_3 DMO_3 0x19 CR1-3 TxOFF_3 TAOS_3 TxClkINV_3 TxLEV_3 Reserved 0x1A...
Page 59: Command Register Cr1-(N)
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 tion. This bit-field is set to "1" if the Channel(n) Digital Writing a "1" to this bit-field configures the Transmitter LOS Detector is currently declaring an LOS condition. to sample the TPData and TNData input pins on the rising edge of TxClk.
Page 60: Ommand Egister Cr2-( )
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 Bit D4 - Reserved Writing a "0" to this bit-field enables the Digital LOS Detector. Writing a "1" to this bit-field disables the Bit D3 - Reserved Digital LOS Detector. Bit D2 - ALOSDIS_(n) (Analog LOS Disable - : If the Digital LOS Detector is disabled, then the Channel(n)) RLOS input pin is only asserted by the ALOS (Analog LOS...
Page 61: Command Register Cr4-(N)
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 This bit-field has no defined functionality Bit D2 - E3 Mode Select - Channel(n) Command Register CR4-(n) This Read/Write bit-field is used to configure Chan- nel(n) to operate in the E3 Mode. The bit-format and default values for Command Reg- ister CR4 are listed below followed by the function of Writing a "0"...
Page 62 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 : Each of these bits is clocked into the SDI input on mand Register at Address [A4, A3, A2, A1, A0] via the rising edge of SClk. the SDO output pin can begin. The Microprocessor Serial Interface outputs this five bit data word (D0 Bit 1 - R/W (Read/Write) Bit through D4) in ascending order with the LSB first on...
Page 63 XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 39. T IGURE IMING IAGRAM FOR THE ICROPROCESSOR ERIAL NTERFACE SClk SClk Hi-Z Hi-Z...
Page 64: Ordering Information
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 2.0.3 ORDERING INFORMATION ACKAGE PERATING TEMPERATURE ANGE XRT73L04AIV 144 Pin Thermally Enhanced TQFP 20 x 20 x 1.4mm -40°C to +85°C Theta-J = 20° C/W Theta-J = 6° C/W HERMAL NFORMATION PACKAGE DIMENSIONS 144 LEAD THIN QUAD FLAT PACK (20 x 20 x 1.4 mm TQFP) rev.
Page 65: Revision History
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo- ration is adequately protected under the circumstances.

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