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Exar XRT73LC03A Manual

3 channel ds3/e3/sts-1 line interface unit
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OCTOBER 2003
GENERAL DESCRIPTION
The XRT73LC03A, 3-Channel, DS3/E3/STS-1 Line
Interface Unit is a low power CMOS version of the
XRT73L03A and consists of three independent line
transmitters and receivers integrated on a single chip
designed for DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73LC03A can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configured to operate in a mode/data
rate that is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73LC03A performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
F
1. XRT73LC03A B
IGURE
E3_(n)
RTIP_(n)
RRing_(n)
REQEN_(n)
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
TTIP_(n)
TRing_(n)
MTIP_(n)
MRing_(n)
DMO_(n)
Notes: 1. (n) = 0, 1, or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
D
LOCK
IAGRAM
STS-1/DS3_(n)
Host/(HW)
RLOL_(n) EXClk_(n)
AGC/
Slicer
Equalizer
Peak
Detector
LOS Detector
Serial
Processor
Loop MUX
Interface
HDB3/
Pulse
B3ZS
Shaping
Encoder
Tx
Device
Control
Monitor
XRT73LC03A
FEATURES
• Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L03A
• Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
• Contains a 4-Wire Microprocessor Serial Interface
• Full Loop-Back Capability
• Transmit and Receive Power Down Modes
• Full Redundancy Support
• Uses Minimum External components
• Single +3.3V Power Supply
• Low power CMOS design
• 5V tolerant I/O
• -40°C to +85°C Operating Temperature Range
• Available in a 120 pin LQFP package
APPLICATIONS
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
• Multiplexers
• ATM Switches
RxOFF
RxClkINV
Clock
Invert
Recovery
Data
HDB3/
Recovery
B3ZS
Decoder
Transmit
Logic
Duty Cycle Adjust
Channel 0 - (n) = 0
Channel 1 - (n) = 1
Channel 2 - (n) = 2
•
•
(510) 668-7000
FAX (510) 668-7017
REV. 1.0.1
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF_(n)
•
www.exar.com

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Summary of Contents for Exar XRT73LC03A

  • Page 1 DS3, E3 or SONET STS-1 applications. • Contains a 4-Wire Microprocessor Serial Interface Each channel of the XRT73LC03A can be configured • Full Loop-Back Capability to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) • Transmit and Receive Power Down Modes or the SONET STS-1 (51.84 Mbps) rates.

  • Page 2: Typical Applications

    XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TYPICAL APPLICATIONS 2. M ATM A IGURE ULTI HANNEL PPLICATION RPOS RPOS RPOS RRPOS RTIP RNEG RNEG RNEG RRNEG RRing RxClk RxClk RxLineClk RRClk Switch/ XRT74L73 XRT71D03 XRT73LC03 MClk TPOS TTIP...

  • Page 3: General Description

    XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 4. P XRT73LC03A 120 P LQFP IGURE IN OUT OF THE IN THE PACKAGE EXDG ND R LO L_2 EXDVDD LC V _2 EXClk_1 R LO S _2 R LO L_0...

  • Page 4: Table Of Contents

    XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TABLE OF CONTENTS GENERAL DESCRIPTION ....................1 ..............................1 EATURES APPLICATIONS ............................1 ..........................2 YPICAL PPLICATIONS : ..................... 2 RANSMIT NTERFACE HARACTERISTICS : ....................... 2 ECEIVE NTERFACE HARACTERISTICS ORDERING INFORMATION ....................3 PIN DESCRIPTIONS (BY FUNCTION) ................
  • Page 5 OMMAND EGISTER 3.7 S ......................46 HUTTING ECEIVE ECTION CR3-( ) ...................... 46 OMMAND EGISTER 4.0 Diagnostic Features of the XRT73LC03A ..................47 4.1 T ......................47 NALOG OCAL 4.2 T ......................48 IGITAL OCAL CR4-( ) ...................... 48...

  • Page 6: Pin Descriptions (By Function)

    (BY FUNCTION) TRANSMIT INTERFACE ESCRIPTION TTIP_0 Transmit TTIP Output - Channel (n): TTIP_1 The XRT73LC03A uses this pin along with TRing_(n) to transmit a bipo- TTIP_2 lar line signal via a 1:1 transformer. TRing_0 Transmit Ring Output - Channel (n): TRing_1...
  • Page 7 SONET STS-1 Modes. The XRT73LC03A is configured to operate in the Hardware Mode. : This pin to should be tied to GND if the XRT73LC03A is going to be operating in the HOST Mode, (internally pulled-down). TxOFF_0 Transmitter OFF Input - Channel (n): TxOFF_1 Setting this input pin "High"...

  • Page 8: Receive Interface

    Equalizer. The guidelines for enabling and disabling the Receive Equal- izer are described in Section 3.2. : This pin is ignored and should be tied to GND if the XRT73LC03A is going to be operating in the HOST Mode, (internally pulled-down).

  • Page 9: Clock Interface

    Register Reset Input (Invert RxClk(n)) Output - Select: REGR/ RxClkINV The function of this pin depends upon whether the XRT73LC03A is oper- ating in the HOST Mode or in the Hardware Mode. : This pin is internally pulled "High". In the HOST-Mode - Register Reset Input: Setting this input pin "Low"...
  • Page 10 The XRT73LC03A ignores this pin if the E3_(n) pin is set to "1". This input pin is ignored if the XRT73LC03A is operating in the HOST Mode. : This pin should be tied to GND if the XRT73LC03A is going to be operating in the HOST Mode, (internally pulled-down). HOST/Hardware Mode Select:...

  • Page 11: Control And Alarm Interface

    The frequency of this "1’s" pattern is determined by TxClk_(n). This input pin is ignored if the XRT73LC03A is operating in the HOST Mode. : This pin should be tied to GND if the XRT73LC03A is going to be operating in the HOST Mode, (internally pulled-down). RLOS_0...
  • Page 12 A "High" on this pin with RLB_(n) also being set to "High" configures Channel (n) to operate in the Digital Local Loop-Back Mode. : This pin is ignored and should be tied to GND if the XRT73LC03A is going to be operating in the HOST Mode.

  • Page 13: Microprocessor Interface

    B3ZS format for STS-1/DS3 operation or in the HDB3 format for E3 operation. : If the XRT73LC03A is operating in the Hardware Mode, this pin setting configures the B3ZS/HDB3 Encoder and Decoder Blocks for all Channels.
  • Page 14 Register Reset Input pin (Invert RxClk(n)) Output - Select): REGR/ RxClkINV The function of this pin depends upon whether the XRT73LC03A is oper- ating in the HOST Mode or in the Hardware Mode. : This pin is internally pulled "High".

  • Page 15: Power And Ground Pins

    XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 POWER AND GROUND PINS PIN # NAME TYPE DESCRIPTION TxAVDD_1 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) TxAGND_1 **** Transmitter Analog Ground - Channel(n) TxAGND_2 **** Transmitter Analog Ground - Channel(n)

  • Page 16: No Connection Pins

    XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 NO CONNECTION PINS PIN # NAME TYPE DESCRIPTION No connection No connection No connection No connection...

  • Page 17: Electrical Characteristics

    Theta-JA 25° C/W Theta-JC 8.5° C/W : The XRT73LC03A is assembled in a thermally dered to the mounting board if desired, but must be electri- enhanced package with an integral Copper Heat Slug. The cally isolated from any V connections.
  • Page 18 RxClk_(n) Clock Rise Time (10% to 90%) RxClk_(n) Clock Fall Time (10% to 90%) Input Capacitance Load Capacitance 2. All XRT73LC03A digital outputs are also TTL 5V OTES compliant. However, these outputs will not drive to 1. All XRT73LC03A digital inputs are designed to be 5V nor will they accept external 5V pull-ups.
  • Page 19 XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 5. T E3, DS3 STS-1 R IGURE RANSMIT ULSE MPLITUDE IRCUIT FOR ATES TYPICAL CHANNEL TTIP_(n) 31.6Ω Channel (n) Channel (n) TxPOS_(n) TPData_(n) TxNEG_(n) TNData_(n) 75Ω TxLineClk_(n) TxClk_(n) 31.6Ω TRing_(n) Only One Channel Shown 6.
  • Page 20 XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED E3 A ARAMETERS PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS Transmit Output Pulse Amplitude 0.90...
  • Page 21 XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED STS-1 A ARAMETERS ONET PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS Transmit Output Pulse Amplitude (Measured with TxLEV=0) 0.65...
  • Page 22 XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED DS3 A ARAMETERS PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS Transmit Output Pulse Amplitude (Measured at 0 feet, TxLEV=0) 0.65...
  • Page 23 XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 Figure 8, Figure 9 and Figure 10 present the Pulse Template requirements for the E3, DS3 and STS-1 Rates. 8. ITU-T G.703 T E3 A IGURE RANSMIT UTPUT ULSE EMPLATE FOR...
  • Page 24 XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 10. B GR-253-CORE T SONET STS-1 A IGURE ELLCORE RANSMIT UTPUT ULSE EMPLATE FOR PPLICATIONS STS-1 Pulse Template Lower Curve Upper Curve -0.2 Time, in UI 11. M IGURE ICROPROCESSOR ERIAL...
  • Page 25 XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED ICROPROCESSOR ERIAL NTERFACE IMING IGURE YMBOL ARAMETER NITS CS Low to Rising Edge of SClk Setup Time...

  • Page 26: System Description

    1. The Microprocessor Serial Interface block is dis- abled. A functional block diagram of the XRT73LC03A E3/ 2. The XRT73LC03A is configured via input pin set- DS3/STS-1 Transceiver IC is presented in Figure 13. tings. The XRT73LC03A contains three separate channels...

  • Page 27: 1.0 Selecting The Data Rate

    1.0 SELECTING THE DATA RATE 1.1 C ONFIGURING HANNEL Each channel within the XRT73LC03A can be config- For the following disscussion the reader should refer ured to support the E3 (34.368 Mbps), DS3 (44.736 toTable 2 to determine the appropriate Address for Mbps) or the SONET STS-1 (51.84 Mbps) rates.
  • Page 28 XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 2: H XRT73LC03A C ABLE EXADECIMAL DDRESSES AND ORMATS OF OMMAND EGISTERS EGISTER ORMAT COMMAND ADDRESS TYPE REGISTER HANNEL 0x00 CR0-0 RLOL_0 RLOS_0 ALOS_0 DLOS_0 DMO_0 0x01 CR1-0 TxOFF_0 TAOS_0 TxClkINV_0...

  • Page 29: 2.0 The Transmit Section

    • TxClk_(n) Figure 13 indicates that the Transmit Section within Figure 14 illustrates the typical interface for the trans- each Channel of the XRT73LC03A consists of the fol- mission of data in a Dual-Rail Format between the lowing blocks: Terminal Equipment and the Transmit Section of the XRT73LC03A.

  • Page 30: Accepting Single-Rail Data From The Terminal Equipment

    TTIP_(n) and TRing_(n) To transmit data in a Single-Rail data from the Termi- output pins. nal Equipment, configure the XRT73LC03A in the HOST Mode. OTES 1. In this mode, the Transmit Logic Block ignores the Write a "1"...

  • Page 31: The Transmit Clock Duty Cycle Adjust Circuitry

    The on-chip Pulse-Shaping circuitry within the Trans- 2.3.1 B3ZS Encoding mit Section of each Channel in the XRT73LC03A If the XRT73LC03A has been configured to operate in generates pulses of the appropriate shapes and the DS3 or SONET STS-1 Modes, then the HDB3/ width to meet the applicable pulse template require- B3ZS Encoder blocks operate in the B3ZS Mode.

  • Page 32: 2.3.2 Hdb3 Encoding

    HDB3 Encoder decides whether to substitute with ei- ther the "000V" or the "B00V" pattern in order to in- If the XRT73LC03A is configured to operate in the E3 sure that an odd number of bipolar pulses exist be- Mode, then the HDB3/B3ZS Encoder blocks operate tween any two consecutive violation pulses.

  • Page 33: The Transmit Pulse Shaping Circuitry

    3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 COMMAND REGISTER CR2-(n) : This method can only be used if the XRT73LC03A is uration of each channel to transmit an output pulse operating in the HOST Mode. which is compliant to either of the following pulse...

  • Page 34: Enabling The Transmit Line Build-Out Circuit

    If the Transmit Line Build-Out circuit is disabled, then a. Operating in the Hardware Mode the XRT73LC03A outputs partially shaped pulses on- Set the TxLEV_(n) input pin to “High". to the line via the TTIP_(n) and TRing_(n) output b.

  • Page 35: Command Register, Cr1-(N)

    Transmit Line Build-Out circuit ial cable are to be terminated with 75 Ohm resistor. by setting the TxLEV_(n) input pin or bit-field to Interface the Transmit Section of the XRT73LC03A in "1". the manner illustrated in Figure 21.

  • Page 36: Transformer Recommendations

    XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TRANSFORMER RECOMMENDATIONS ARAMETER ALUE Turns Ratio Primary Inductance 40µH Isolation Voltage 1500Vrms Leakage Inductance 0.6µH UMBER ENDOR NSULATION ACKAGE PE-68629 Pulse 3000V Large Thru-Hole PE-65966 Pulse 1500V Small Thru-Hole PE-65967 Pulse...

  • Page 37: 3.0 The Receive Section

    XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 3.0 THE RECEIVE SECTION line and encode it back into the TTL/CMOS format where it can be received and processed by the Termi- Figure 13 indicates the Receive Section consists of nal Equipment.

  • Page 38: The Receive Equalizer Block

    DSX-3 or STSX-1 Pulse Template requirements. For state to set the Receive Equalizer when the overall the XRT73LC03A device, this is achieved by setting cable-length, from the local Receiving Terminal to the the TXLEV_(n) input pin or bit-field to the appropriate remote Transmitting Terminal is NOT known.

  • Page 39: Command Register Cr2-(N)

    When the System Manufacturer is interfacing the Re- In E3 System installation, it is recommended that the ceive Section of the XRT73LC03A to the Cross-Con- Receive Equalizer of the XRT73LC03A device be en- nect, they should be aware of the following facts: abled by pulling the REQEN_(n) input pins “High”...

  • Page 40: Clock Recovery Pll

    Dual-Rail data and check for the occurrence If the XRT73LC03A is configured to operate in the E3 of either a "000V" or a "B00V" pattern. If the HDB3 Mode, then each of the HDB3/B3ZS Decoding Blocks...

  • Page 41: 3.4.3 Configuring The Hdb3/B3Zs Decoder

    The channel declares the LOS condition by blocks in the XRT73LC03A and configure the toggling its respective RLOS_(n) output pin “High” XRT73LC03A to transmit and receive in an AMI for- and by setting its corresponding RLOS_(n) bit field in mat, pull the ENDECDIS input pin "High".

  • Page 42: The Los Declaration/Clearance Criteria For E3 Applications

    Figure 26 illustrates the signal levels at which for E3 Applications each channel of the XRT73LC03A declares and When the XRT73LC03A is operating in the E3 Mode, clears LOS. a given channel declares an LOS Condition if its re- 26.

  • Page 43: The Los Declaration/Clearance Criteria For Ds3 And Sts-1 Applications

    1. The Analog LOS (ALOS) Declaration/Clearance for DS3 and STS-1 Applications Criteria When the XRT73LC03A is operating in the DS3 or A channel declares an Analog LOS (ALOS_(n)) Con- STS-1 Mode, then each channel declares and clears dition if the amplitude of the incoming line signal LOS based upon the following two criteria.

  • Page 44: Command Register Cr0-(N)

    XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 If the XRT73LC03A is operating in the HOST Mode, monitored by reading in the contents of Command the state of ALOS_(n) of Channel(n) can be polled or Register CR0. . COMMAND REGISTER CR0-(n)

  • Page 45: Command Register Cr3-( N )

    Muting upon LOS feature globally for all channels. nal. b. Operating in the HOST Mode. This feature is available whenever XRT73LC03A is The Muting upon LOS feature for each Channel can operating in the HOST Mode or Hardware Mode. be enabled by writing a "1" into the LOSMUT_(n) bit- a.
  • Page 46 Setting the RxClkINV pin “High” results in all chan- ty pulse in the incoming line signal via the RTIP_(n) nels of the XRT73LC03A to output the recovered data and RRing_(n) input pins, then the channel(n) pulses on RPOS_(n) and RNEG_(n) on the falling edge of its corresponding RNEG_(n) output pin “High".

  • Page 47: Command Register Cr3-(N)

    RPOS_(n) and RxClk_(n) output pins, as illustrat- pulling the (SR/DR) pin to VDD. ed in Figure 31 and Figure 32. : When the XRT73LC03A is operating in the Hard- ware Mode, the setting of the (SR/DR) input pin applies glo- b. Operating in the Hardware Mode bally to all channels.

  • Page 48: Shutting Off The Receive Section

    “High". Turn on the Receiver Sections by The Receive Section of each channel in the pulling the RxOFF input pin to “Low". XRT73LC03A can be shut off. This feature may b. Operating in the HOST Mode come in handy in some redundant system designs.

  • Page 49: Diagnostic Features Of The Xrt73Lc03A

    This data is processed through the Transmit Clock Duty Cycle Adjust PLL and the HDB3/B3ZS The XRT73LC03A supports equipment diagnostic ac- Encoder. Finally, this data is output to the line via the tivities by supporting the following Loop-Back modes TTIP_(n) and TRing_(n) output pins.

  • Page 50: The Digital Local Loop -Back Mode

    RTIP and RRing in- COMMAND REGISTER CR4-(n) put pins. The Transmitting Terminal Equipment trans- mits clock and data into the XRT73LC03A via the TP- Data, TNData and TxClk input pins. This data is pro- STS-1/DS3_(n)

  • Page 51: The Remote Loop -Back Mode

    XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 To configure Channel (n) to operate in the Digital Lo- put to the Receive Terminal Equipment via the RPOS, cal Loop-Back Mode, pull both the LLB input pin and RNEG and RxClk output pins. Additionally, this data the RLB input pin "High".

  • Page 52: T Xoff Features

    EATURES COMMAND REGISTER CR1-(n) The Transmit Section of each Channel in the XRT73LC03A can be shut off. When this feature is invoked, the Transmit Section of the configured chan- TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n) nel is shut-off and the Transmit Output signals (e.g., TTIP_(n) and TRing_(n)) is tri-stated.

  • Page 53: The Taos (Transmit All One S) Feature

    Command Registers to "1". DS3/E3/STS-1 Line Interface Unit IC are used to con- : When this feature is activated, the Transmit Section figure the XRT73LC03A into a wide-variety of modes. of the configured channel overwrites the Terminal Equip- This section discusses the following: ment data with this all “1’s"...
  • Page 54 The Command Registers are either Read-Only (RO) type of registers or Read/Write (R/W) type of regis- The register addresses are presented in the Hexa- ters. Each channel of the XRT73LC03A has eight decimal format. command registers, CR0-(n) through CR7-(n) where...

  • Page 55: Description Of Bit -Fields For Each Command Register

    XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 (n) = 0, 1 or 2. The associated addresses for each This Read-Only bit-field indicates whether or not the channel are presented in , (repeated as Table 7). Channel(n) Digital LOS Detector is currently declar- ing an LOS condition.

  • Page 56: Command Register Cr2-(N)

    This Read/Write bit-field is used to enable or disable nel(n) is less than 225 feet. the Channel(n) Transmit Line Build-Out circuit. This bit-field is active only if the XRT73LC03A is con- Setting this bit-field "High" disables the Channel(n) figured to operate in the DS3 or SONET STS-1 Line Build-Out circuit.

  • Page 57: Command Register Cr4-(N)

    Encoder and Decoder blocks. Writing a "0" to this bit- field disables the B3ZS/HDB3 Encoder and Decoder blocks. COMMAND REGISTER CR4-(n) : This Encoder/Decoder performs HDB3 Encoding/ Decoding if the XRT73LC03A is operating in the E3 Mode. Otherwise, it performs B3ZS Encoding/Decoding. Reserved STS-1/DS3_(n) E3_(n) LLB_(n) RLB_(n) .Writing a "1"...

  • Page 58: Operating The Microprocessor Serial Interface

    This interface Write operation. The address selects the Command consists of the following signals: Register in the XRT73LC03A that the user is either reading data from or writing data to. The address bits • CS - Chip Select (Active Low) must be supplied to the SDI input pin in ascending or- •...
  • Page 59 XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 the desired eight bit data word to the SDI input pin via from and/or writing data to this combined signal. This the Microprocessor Serial Interface. The Micropro- simplification is possible because only one of these cessor Serial Interface latches the value on the SDI signals are active at any given time.

  • Page 60: Ordering Information

    XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ORDERING INFORMATION ACKAGE PERATING TEMPERATURE ANGE XRT73LC03AIV 120 Pin LQFP 14mm X 20mm C to +85 Theta-J = 25°C/W Theta-J =8.5°C/W HERMAL NFORMATION PACKAGE DIMENSIONS 120 LEAD QUAD FLAT PACK 14mm X 20 mm, LQFP Rev.

  • Page 61: Revision History

    EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo- ration is adequately protected under the circumstances.

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