Exar XRT73L03 Manual

3 channel ds3/e3/sts-1 line interface unit

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MARCH 2001

GENERAL DESCRIPTION

The XRT73L03, 3-Channel, DS3/E3/STS-1 Line In-

terface Unit consists of three independent line trans-

mitters and receivers integrated on a single chip de-

signed for DS3, E3 or SONET STS-1 applications.

Each channel of the XRT73L03 can be configured to

support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or

the SONET STS-1 (51.84 Mbps) rates. Each channel

can be configured to operate in a mode/data rate that

is independent of the other channels.

In the transmit direction, each channel encodes input

data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-

mat and converts the data into the appropriate pulse

shapes for transmission over coaxial cable via a 1:1

transformer.

In the receive direction, the XRT73L03 performs

equalization on incoming signals, performs Clock Re-

covery, decodes data from either B3ZS or HDB3 for-

mat, converts the receive data into TTL/CMOS for-

mat, checks for LOS or LOL conditions and detects

and declares the occurrence of Line Code Violations.

FEATURES

1. XRT73L03 B

IGURE

LOCK

E3_(n)

RTIP_(n)

RRing_(n)

Equalizer

REQEN_(n)

LOSTHR_(n)

SDI

SDO

Processor

SClk

Interface

REGR

TTIP_(n)

TRing_(n)

MTIP_(n)

MRing_(n)

DMO_(n)

Notes: 1. (n) = 0, 1, or 2 for respective Channels

2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.

Exar

Corporation 48720 Kato Road, Fremont CA, 94538

IAGRAM

STS-1/DS3_(n)

Host/(HW)

RLOL_(n) EXClk_(n)

AGC/

Slicer

Peak

Detector

LOS Detector

Serial

Loop MUX

HDB3/

Pulse

B3ZS

Shaping

Encoder

Device

Control

Monitor

3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

• Meets E3/DS3/STS-1 Jitter Tolerance Require-

ments

• Contains a 4-Wire Microprocessor Serial Interface

• Full Loop-Back Capability

• Transmit and Receive Power Down Modes

• Full Redundancy Support

• Uses Minimum External components

• Single +3.3V Power Supply

• 5V tolerant I/O

• -40°C to +85°C Operating Temperature Range

• Available in a Thermally Enhanced 120 pin TQFP

package

APPLICATIONS

• Digital Cross Connect Systems

• CSU/DSU Equipment

• Routers

• Fiber Optic Terminals

• Multiplexers

• ATM Switches

RxOFF

RxClkINV

Clock

Invert

Recovery

Data

Recovery

Decoder

Transmit

Logic

Duty Cycle Adjust

Channel 0 - (n) = 0

Channel 1 - (n) = 1

Channel 2 - (n) = 2

•

(510) 668-7000

FAX (510) 668-7017

XRT73L03

RxClk_(n)

RPOS_(n)

HDB3/

B3ZS

RNEG_(n)

LCV_(n)

ENDECDIS

RLOS_(n)

LLB_(n)

RLB_(n)

TAOS_(n)

TPData_(n)

TNData_(n)

TxClk_(n)

TxLEV_(n)

TxOFF_(n)

•

www.exar.com

REV. 1.1.0

Table of Contents

Summary of Contents for Exar XRT73L03

Page 1 • Full Loop-Back Capability signed for DS3, E3 or SONET STS-1 applications. • Transmit and Receive Power Down Modes Each channel of the XRT73L03 can be configured to • Full Redundancy Support support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or •...
Page 2 áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 TYPICAL APPLICATIONS 2. M ATM A IGURE ULTI HANNEL PPLICATION RPOS RPOS RPOS RRPOS RTIP RNEG RNEG RNEG RRNEG RRing RxClk RxClk RxLineClk RRClk Switch/ XRT72L73 XRT71D03...
Page 3: General Description
áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 4. P XRT73L03 120 P TQFP IGURE IN OUT OF THE IN THE PACKAGE EXDGND RLOL_2 EXDVDD LCV_2 RLOS_2 EXClk_1 RLOL_0 REQEN_2 STS1/DS3_2 LCV_0 RLOS_0 E3_2 EXClk_2...
Page 4: Table Of Contents
áç áç áç áç XRT73L03 3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 TABLE OF CONTENTS GENERAL DESCRIPTION ....................1 ..............................1 EATURES APPLICATIONS ............................1 ..........................2 YPICAL PPLICATIONS : ..................... 2 RANSMIT NTERFACE HARACTERISTICS : ....................... 2 ECEIVE...
Page 5 OMMAND EGISTER 3.7 S ......................45 HUTTING ECEIVE ECTION CR3-( ) ...................... 45 OMMAND EGISTER 4.0 Diagnostic Features of the XRT73L03 .................... 46 4.1 T ......................46 NALOG OCAL 4.2 T ......................47 IGITAL OCAL CR4-( ) ...................... 47...
Page 6: Pin Descriptions (By Function)
TNData_(n) input pins. By default, the XRT73L03 is configured to sam- ple these two pins on the falling edge of this signal. : If the XRT73L03 is operating in the HOST Mode, then the device can be configured to sample the TPData_(n) and TNData_(n) input pins on either the rising or falling edge of TxClk_(n).
Page 7 The XRT73L03 is configured to operate in either the DS3 or SONET STS-1 Modes. The XRT73L03 is configured to operate in the Hardware Mode. : This pin to should be tied to GND if the XRT73L03 is going to be operating in the HOST Mode, (internally pulled-down). TxOFF_0...
Page 8: Receive Interface
Equalizer. The guidelines for enabling and disabling the Receive Equal- izer are described in Section 3.2. : This pin is ignored and should be tied to GND if the XRT73L03 is going to be operating in the HOST Mode, (internally pulled-down).
Page 9: Clock Interface
Register Reset Input pin (Invert RxClk(n)) Output - Select): REGR/ RxClkINV The function of this pin depends upon whether the XRT73L03 is operat- ing in the HOST Mode or in the Hardware Mode. : This pin is internally pulled "High".
Page 10 The XRT73L03 ignores this pin if the E3_(n) pin is set to "1". This input pin is ignored if the XRT73L03 is operating in the HOST Mode. : This pin should be tied to GND if the XRT73L03 is going to be operating in the HOST Mode, (internally pulled-down).
Page 11: Control And Alarm Interface
The frequency of this "1’s" pattern is determined by TxClk_(n). This input pin is ignored if the XRT73L03 is operating in the HOST Mode. : This pin should be tied to GND if the XRT73L03 is going to be operating in the HOST Mode, (internally pulled-down).
Page 12 A "High" on this pin with RLB_(n) also being set to "High" configures Channel (n) to operate in the Digital Local Loop-Back Mode. : This pin is ignored and should be tied to GND if the XRT73L03 is going to be operating in the HOST Mode.
Page 13: Microprocessor Interface
B3ZS format for STS-1/DS3 operation or in the HDB3 format for E3 oper- ation. : If the XRT73L03 is operating in the Hardware Mode, this pin set- ting configures the B3ZS/HDB3 Encoder and Decoder Blocks for all Channels.
Page 14 Register Reset Input pin (Invert RxClk(n)) Output - Select): REGR/ RxClkINV The function of this pin depends upon whether the XRT73L03 is operat- ing in the HOST Mode or in the Hardware Mode. : This pin is internally pulled "High".
Page 15: Power And Ground Pins
áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 POWER AND GROUND PINS PIN # NAME TYPE DESCRIPTION TxAVDD_1 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) TxAGND_1 **** Transmitter Analog Ground - Channel(n) TxAGND_2...
Page 16: N O Connection Pins
áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 NO CONNECTION PINS PIN # NAME TYPE DESCRIPTION No connection No connection No connection No connection...
Page 17: Electrical Characteristics
áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 ELECTRICAL CHARACTERISTICS = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS UNLESS OTHERWISE SPECIFIED YMBOL ARAMETER NITS DC Electrical Characteristics Digital DC Supply Voltage 3.135 3.465...
Page 18 RxClk_(n) Clock Fall Time (10% to 90%) Input Capacitance Load Capacitance 2. All XRT73L03 digital outputs are also TTL 5V com- OTES pliant. However, these outputs will not drive to 5V 1. All XRT73L03 digital inputs are designed to be TTL nor will they accept external 5V pull-ups.
Page 19 áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 5. T E3, DS3 STS-1 R IGURE RANSMIT ULSE MPLITUDE IRCUIT FOR ATES TYPICAL CHANNEL TTIP_(n) 31.6 Ω Channel (n) Channel (n) TxPOS_(n) TPData_(n) TxNEG_(n) TNData_(n) 75 Ω...
Page 20 áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED E3 A ARAMETERS PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS...
Page 21 áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 ), (T = 25 ° C, V = 3.3V + 5%, LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED STS-1 A ARAMETERS ONET PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER...
Page 22 áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 ), (T = 25 C, V = 3.3V + 5%, ° LECTRICAL HARACTERISTICS ONTINUED UNLESS OTHERWISE SPECIFIED DS3 A ARAMETERS PPLICATION RANSMIT HARACTERISTICS IGURE YMBOL ARAMETER NITS Transmit Output Pulse Amplitude 0.68...
Page 23: Absolute Maximum Ratings
23° C/W Theta-JC 7° C/W : The XRT73L03 is assembled in a thermally GND connections of the device. This Heat Slug can be sol- enhanced package with an integral Copper Heat Slug. The dered to the mounting board if desired, but must be electri-...
Page 24 áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 8. M IGURE ICROPROCESSOR ERIAL NTERFACE TRUCTURE SClk High Z High Z 3. R/W = "0" for "Write" Operations OTES 1. A5 is always "0". 4. A shaded pulse, denotes a “don’t care” value.
Page 25: System Description
1. The Microprocessor Serial Interface block is dis- abled. A functional block diagram of the XRT73L03 E3/DS3/ 2. The XRT73L03 is configured via input pin set- STS-1 Transceiver IC is presented in Figure 10. The tings. XRT73L03 contains three separate channels with...
Page 26: Selecting The Data Rate
1.0 SELECTING THE DATA RATE 1.1 C ONFIGURING HANNEL Each channel within the XRT73L03 can be config- For the following disscussion the reader should refer ured to support the E3 (34.368 Mbps), DS3 (44.736 toTable 2 to determine the appropriate Address for Mbps) or the SONET STS-1 (51.84 Mbps) rates.
Page 27 áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 2: H XRT73L03 C ABLE EXADECIMAL DDRESSES AND ORMATS OF OMMAND EGISTERS EGISTER ORMAT COMMAND ADDRESS TYPE REGISTER HANNEL 0x00 CR0-0 RLOL_0 RLOS_0 ALOS_0 DLOS_0 DMO_0 0x01...
Page 28: The Transmit Section
• TxClk_(n) Figure 10 indicates that the Transmit Section within Figure 11 illustrates the typical interface for the trans- each Channel of the XRT73L03 consists of the follow- mission of data in a Dual-Rail Format between the ing blocks: Terminal Equipment and the Transmit Section of the •...
Page 29: Accepting Single-Rail Data From The Terminal Equipment
TTIP_(n) and TRing_(n) To transmit data in a Single-Rail data from the Termi- output pins. nal Equipment, configure the XRT73L03 in the HOST Mode. OTES 1. In this mode, the Transmit Logic Block ignores the Write a "1"...
Page 30: The Transmit Clock Duty Cycle Adjust Circuitry
CUITRY The on-chip Pulse-Shaping circuitry within the Trans- 2.3.1 B3ZS Encoding mit Section of each Channel in the XRT73L03 gener- If the XRT73L03 has been configured to operate in ates pulses of the appropriate shapes and width to the DS3 or SONET STS-1 Modes, then the HDB3/ meet the applicable pulse template requirements.
Page 31: Hdb3 Encoding
HDB3 Encoder decides whether to substitute with ei- ther the "000V" or the "B00V" pattern in order to in- If the XRT73L03 is configured to operate in the E3 sure that an odd number of bipolar pulses exist be- Mode, then the HDB3/B3ZS Encoder blocks operate tween any two consecutive violation pulses.
Page 32: Command Register Cr2-(N)
ENDECDIS_(n) ALOSDIS_(n) DLOSDIS_(n) REQEN_(n) : This method can only be used if the XRT73L03 is uration of each channel to transmit an output pulse operating in the HOST Mode. which is compliant to either of the following pulse If either of these methods are used to disable the...
Page 33: Enabling The Transmit Line Build-Out Circuit
If the Transmit Line Build-Out circuit is disabled, then a. Operating in the Hardware Mode the XRT73L03 outputs partially shaped pulses onto Set the TxLEV_(n) input pin to “High". the line via the TTIP_(n) and TRing_(n) output pins.
Page 34: Command Register, Cr1-(N)
75 Ohm resistor. feet, disable the Transmit Line Build-Out circuit by Interface the Transmit Section of the XRT73L03 in setting the TxLEV_(n) input pin or bit-field to "1". the manner illustrated in Figure 18.
Page 35: Transformer Vendor Information
áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 FAX: 44-1483-401701 Transformer Recommendations Asia ARAMETER ALUE 150 Kampong Ampat #07-01/02 Turns Ratio KA Centre Primary Inductance 4µH Singapore 368324 Isolation Voltage 1500Vrms Tel: 65-287-8998 Leakage Inductance 0.06µH...
Page 36: The Receive Equalizer Block
RNEG_(n) RxClk_(n) RxClk_(n) 37.4 Ω RRing_(n) Only One Channel Shown Figure 20 presents the recommended schematic for capacitive-coupling each Receive Section of the XRT73L03 to the line. 20. R XRT73L03 IGURE ECOMMENDED CHEMATIC FOR NTERFACING THE ECEIVE ECTION OF THE...
Page 37: Guidelines For Setting The Receive Equalizer
DSX-3 or STSX-1 Pulse Template requirements. For 3.2.1.1 If the Overall Cable Length is NOT the XRT73L03 device, this is achieved by setting the Known TXLEV_(n) input pin or bit-field to the appropriate lev- This section presents recommendations on what...
Page 38: Command Register Cr2-(N)
Requirements per Bellcore GR-499-CORE for : The results of extensive testing indicates that when the Receive Equalizer is enabled, the XRT73L03 device is DS3 applications, or Bellcore GR-253-CORE for capable of receiving an E3 line signal with anywhere from 0 STS-1 applications.
Page 39: The Training Mode
EXClk_(n) input pin exceeds 0.5%, then the channel If the XRT73L03 is configured to operate in the DS3 operates in the Training Mode. When the channel is or STS-1 Modes, then the HDB3/B3ZS Decoding operating in the Training Mode, it does the following: Blocks performs B3ZS Decoding.
Page 40: Configuring The Hdb3/B3Zs Decoder
RNEG Data : If the HDB3 Decoder detects any bipolar violation The XRT73L03 can enable or disable the HDB3/ (e.g., "V") pulses that is not in accordance with the HDB3 B3ZS Decoder blocks by either of the following Line Code format, or if the HDB3 Decoder detects a string means.
Page 41: Command Register Cr2
LEARANCE In general, the LOS Declaration/Clearance scheme Each channel of the XRT73L03 contains circuitry that that is employed in the XRT73L03 is based upon ITU- monitors the following two parameters associated T Recommendation G.775 for both E3 and DS3 appli- with the incoming line signals.
Page 42: The Los Declaration/Clearance Criteria For Ds3 And Sts-1 Applications
1. The Analog LOS (ALOS) Declaration/Clearance for DS3 and STS-1 Applications Criteria When the XRT73L03 is operating in the DS3 or STS- A channel declares an Analog LOS (ALOS_(n)) Con- 1 Mode, then each channel declares and clears LOS dition if the amplitude of the incoming line signal based upon the following two criteria.
Page 43: Command Register Cr0
Level to Declare ALOS levels, as specified inTable 5. Monitoring the State of ALOS_(n) Clearing ALOS_(n) If the XRT73L03 is operating in the HOST Mode, the A channel(n) clears ALOS_(n) whenever the ampli- state of ALOS_(n) of Channel(n) can be polled or...
Page 44: Muting The Recovered Data While The Los Is Being Declared
COMMAND REGISTER CR0-(N) Disabling the DLOS Detector For debugging purposes, it is useful to disable the DLOS_(n) detector. If the XRT73L03 is operating in RLOL_(n) RLOS_(n) ALOS_(n) DLOS_(n) DMO_(n) the HOST Mode, the DLOS Detector can be disabled by writing a “1” into the DLOSDIS_(n) bit-field in Com- Read Only Read Only Read Only Read Only Read Only mand Register CR2.
Page 45 Setting the RxClkINV pin “High” results in all chan- ty pulse in the incoming line signal via the RTIP_(n) nels of the XRT73L03 to output the recovered data on and RRing_(n) input pins, then the channel(n) pulses RPOS_(n) and RNEG_(n) on the falling edge of its corresponding RNEG_(n) output pin “High".
Page 46: Command Register Cr3-(N)
RPOS_(n) and RxClk_(n) output pins, as illustrat- the (SR/DR) pin to VDD. ed in Figure 29 and Figure 30. : When the XRT73L03 is operating in the Hardware Mode, the setting of the (SR/DR) input pin applies globally b. Operating in the Hardware Mode to all channels.
Page 47: Shutting Off The Receive Section
“High". Turn on the Receiver Sections by The Receive Section of each channel in the pulling the RxOFF input pin to “Low". XRT73L03 can be shut off. This feature may come in b. Operating in the HOST Mode handy in some redundant system designs. Particu- Shut off the Receive Sections by writing a "1"...
Page 48: Diagnostic Features Of The Xrt73L03
áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 4.0 DIAGNOSTIC FEATURES OF THE XRT73L03 pins. This data is processed through the Transmit Clock Duty Cycle Adjust PLL and the HDB3/B3ZS The XRT73L03 supports equipment diagnostic activi- Encoder. Finally, this data is output to the line via the ties by supporting the following Loop-Back modes TTIP_(n) and TRing_(n) output pins.
Page 49: He Igital Ocal Oop Ack Ode
RTIP and RRing input COMMAND REGISTER CR4-(n) pins. The Transmitting Terminal Equipment transmits clock and data into the XRT73L03 via the TPData, TNData and TxClk input pins. This data is processed STS-1/DS3_(n) E3_(n)
Page 50: The Remote Loop -Back Mode
áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 To configure Channel (n) to operate in the Digital Lo- put to the Receive Terminal Equipment via the RPOS, cal Loop-Back Mode, pull both the LLB input pin and RNEG and RxClk output pins.
Page 51: T Xoff Features
EATURES COMMAND REGISTER CR1-(n) The Transmit Section of each Channel in the XRT73L03 can be shut off. When this feature is in- voked, the Transmit Section of the configured channel TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n) is shut-off and the Transmit Output signals (e.g., TTIP_(n) and TRing_(n)) is tri-stated.
Page 52: The Taos (Transmit All One S) Feature
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n) Output) signal toggles "High". : The Transmit Drive Monitor circuit does not have to be used to operate the Transmit Section of the XRT73L03. Terminate the all “1’s" pattern by writing to Command This is purely a diagnostic feature.
Page 53 The Command Registers are either Read-Only (RO) type of registers or Read/Write (R/W) type of regis- The register addresses are presented in the Hexa- ters. Each channel of the XRT73L03 has eight com- decimal format. mand registers, CR0-(n) through CR7-(n) where (n) =...
Page 54: Description Of Bit -Fields For Each Command Register
áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 0, 1 or 2. The associated addresses for each channel This Read-Only bit-field indicates whether or not the are presented in , (repeated as Table 7). Channel(n) Digital LOS Detector is currently declar- ing an LOS condition.
Page 55: Command Register Cr2-(N)
This Read/Write bit-field is used to enable or disable nel(n) is less than 225 feet. the Channel(n) Transmit Line Build-Out circuit. This bit-field is active only if the XRT73L03 is config- Setting this bit-field "High" disables the Channel(n) ured to operate in the DS3 or SONET STS-1 Modes.
Page 56: Command Register Cr4-(N)
Encoder and Decoder blocks. Writing a "0" to this bit- field disables the B3ZS/HDB3 Encoder and Decoder blocks. COMMAND REGISTER CR4-(N) : This Encoder/Decoder performs HDB3 Encoding/ Decoding if the XRT73L03 is operating in the E3 Mode. Otherwise, it performs B3ZS Encoding/Decoding. Reserved STS-1/DS3_(n) E3_(n) LLB_(n) RLB_(n) .Writing a "1"...
Page 57: Operating The Microprocessor Serial Interface
Write operation. The address selects the Command The XRT73L03 Serial Interface is a simple four wire Register in the XRT73L03 that the user is either read- interface that is compatible with many of the micro- ing data from or writing data to. The address bits controllers available in the market.
Page 58 áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 input pin on the rising edge of SClk. Apply this word simplification is possible because only one of these (D0 through D7) serially, in ascending order with the signals are active at any given time.
Page 59: Ordering Information
áç áç áç áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.1.0 ORDERING INFORMATION ACKAGE PERATING TEMPERATURE ANGE XRT73L03IV 120 Pin Thermally Enhanced TQFP 14mm X 20mm C to +85 Theta-J = 23° C/W Theta-J =7° C/W HERMAL NFORMATION...
Page 60: Revision History
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo- ration is adequately protected under the circumstances.

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