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Lattice Semiconductor OpenLDI/FPD-LINK/LVDS User Manual

Receiver interface ip
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OpenLDI/FPD-LINK/LVDS Receiver
Interface IP
User Guide
FPGA-IPUG-02021-1.1
April 2019

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Summary of Contents for Lattice Semiconductor OpenLDI/FPD-LINK/LVDS

  • Page 1 OpenLDI/FPD-LINK/LVDS Receiver Interface IP User Guide FPGA-IPUG-02021-1.1 April 2019...

  • Page 2: Table Of Contents

    Revision History .................................. 44 © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 3 Figure 5.9. IP Regeneration in Clarity Designer ........................40 © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 4 ............................42 © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 5: Introduction

    Active HDL™ 10.3 Lattice Edition © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 6: Features

    _io are bidirectional signals © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 7: Functional Descriptions

    © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 8 Output horizontal sync for parallel interface. © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 9: Interface And Timing Diagrams

    Figure 2.2. OpenLDI/FPD-LINK/LVDS Input Bus Waveform © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 10: Figure 2.3. Single Channel Openldi/Fpd-Link/Lvds Input Bus Waveform For Rgb888 Format

    Figure 2.3. Single Channel OpenLDI/FPD-LINK/LVDS Input Bus Waveform for RGB888 Format © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 11: Figure 2.4. Dual Channel Openldi/Fpd-Link/Lvds Input Bus Waveform For Rgb888 Format

    Figure 2.5. Single Channel OpenLDI/FPD-LINK/LVDS Input Bus Waveform for RGB666 Format © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 12: Figure 2.6. Dual Channel Openldi/Fpd-Link/Lvds Input Bus Waveform For Rgb666 Format

    LVDS serial data to pixel format. © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 13: Figure 2.7. Input To Output Waveform For Single Channel Openldi/Fpd-Link/Lvds, Rx Gear 7

    Figure 2.8. Input to Output Waveform for Single Channel OpenLDI/FPD-LINK/LVDS, Rx Gear 14 © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 14: Figure 2.9. Input To Output Waveform For Dual Channel Openldi/Fpd-Link/Lvds, Rx Gear 7

    Figure 2.9. Input to Output Waveform for Dual Channel OpenLDI/FPD-LINK/LVDS, Rx Gear 7 © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 15: Figure 2.10. Input To Output Waveform For Dual Channel Openldi/Fpd-Link/Lvds, Rx Gear 14

    Figure 2.11. Output Pixel Data RGB Arrangement © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 16: Figure 2.12. Output Pixel Data Arrangement For Single Channel Openldi/Fpd-Link/Lvds

    Figure 2.13. Output Pixel Data Arrangement for Dual Channel OpenLDI/FPD-LINK/LVDS © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 17: Clock, Reset And Initialization

    ∗ ����. ���� ���� ��ℎ���������� © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 18: Design And Module Description

    Figure 2.15. FPD-Link Rx Wrapper Block Diagram © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 19: Fpd-Link Rx Module

    © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 20: Table 2.4. Fpd-Link Rx Pin List Summary

    (via BW_ALIGN) © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 21: Table 2.5. Fpd-Link Rx Parameter List

    4 – RGB888 © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 22: Lvds71 Ddr Group Module

    Figure 2.17. LVDS71 DDR Group Block Diagram © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 23: Gddr Sync Module

    Figure 2.18. GDDR_SYNC Block Diagram © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 24: Bw Align Module

    Figure 2.21. ECLKSYNC Block Diagram © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 25: Gpll

    Figure 2.23. LVDS71 Pixel Map Block Diagram © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 26: Test Mode Module

    © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 27: Figure 2.24. Test Mode Block Diagram

    14 – 1:14 Gearing © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 28: Synchronizer Module

    Figure 2.26. Synchronizer Timing Diagram © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 29: Compiler Directives And Parameter Settings

    RGB666 © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 30: Compiler Directives

    `define MISC_ON © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 31: Debug Features

    7. tstmode_err_o is asserted if data mismatch is encountered. © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 32: Ip Generation And Evaluation

    Lattice Diamond Clarity Designer and how to run simulation, synthesis and hardware evaluation. 5.1. Licensing the IP The OpenLDI/FPD-LINK/LVDS Receiver Interface IP is available free of charge, but an IP-specific license is required to enable full, unrestricted use of the OpenLDI/FPD-LINK/LVDS Receiver Interface IP in a complete, top level design.

  • Page 33: Generating Ip In Clarity Designer

    Figure 5.2. Starting Clarity Designer from Diamond Design Environment © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 34: Figure 5.3. Configuring Openldi/Fpd-Link/Lvds Receiver Interface Ip In Clarity Designer

    For detailed instructions on how to use the Clarity Designer, refer to the Lattice Diamond software user guide. © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 35: Generated Ip Directory Structure And Files

    Figure 5.5. OpenLDI/FPD-LINK/LVDS Receiver Interface IP Directory Structure © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 36: Table 5.1. Files Generated In Clarity Designer

    Template for instantiating the generated soft IP top-level in another user-created top module. Aside from the files listed in the tables, most of the files required to evaluate the OpenLDI/FPD-LINK/LVDS Receiver Interface IP are available under the directory \<fpdlinkrx_eval>, including the simulation model. Lattice Diamond project files are also included under the folder at \<fpdlinkrx_eval>\<instance_name>\impl\lifmd\<synthesis_tool>\.

  • Page 37: Running Functional Simulation

    Number of bytes sent per line © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 38: Simulation Strategies

    Figure 5.7. Two Rx Channels Configuration © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 39: Instantiating The Ip

    5. Implement the complete design via the standard Diamond user interface flow. © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 40: Hardware Evaluation

    Clarity Designer regenerates all the instances which are reconfigured. © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 41: References

    Submit a technical support case through www.latticesemi.com/techsupport. © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 42: Appendix A. Resource Utilization

    Performance and utilization data target an LIF-MD6000-6MG81I device using Lattice Diamond 3.9 and Lattice Synthesis Engine software. Performance may vary when using a different software version or targeting a different device density or speed grade within the CrossLink family. This does not show all possible configurations of the OpenLDI/FPD-LINK/LVDS Receiver Interface IP. The f values are based on internal pixel clock.

  • Page 43: Appendix B. What Is Not Supported

    For Dual Channel configuration, only the clock from Channel 0 is used. © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 44: Revision History

    Initial release. © 2017-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 45 www.latticesemi.com...

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