Table of Contents
Advertisement
www.ti.com
TAS5142 Block Diagram
FUNCTIONAL BLOCK DIAGRAM
OTW
Internal Pullup
Resistors to VREG
SD
M1
Protection
M2
and
I/O Logic
M3
RESET_AB
RESET_CD
PWM
PWM_D
Ctrl.
Timing
Rcv.
PWM
PWM_C
Ctrl.
Timing
Rcv.
PWM
PWM_B
Ctrl.
Timing
Rcv.
PWM
PWM_A
Ctrl.
Timing
Rcv.
SLES126B – DECEMBER 2004 – REVISED MAY 2005
VDD
Under-
4
voltage
Protection
VREG
VREG
Power
On
Reset
AGND
Temp.
Sense
GND
Overload
I
OC_ADJ
sense
Protection
GVDD_D
BST_D
PVDD_D
Gate
OUT_D
Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_D
GVDD_C
BST_C
PVDD_C
Gate
OUT_C
Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_C
GVDD_B
BST_B
PVDD_B
Gate
OUT_B
Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_B
GVDD_A
BST_A
PVDD_A
Gate
OUT_A
Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_A
TAS5142
TAS5558 (MAIN: IC40)
TAS5558 Pin Discriptions
www.ti.com
2.1.2 Pin Descriptions
PIN
NAME
ASEL_EMO2
AVDD
AVDD_PWM
AVSS
AVSS_PWM
BKND_ERR
DVDD1
DVDD2
DVSS1
DVSS2
EMO1
HP_SEL
LRCLK
LRCLKO /
LRCKIN_2
MLCK
MUTE
OSCRES
PDN
PLL_FLTM
PLL_FLTP
PSVC/MCLKO
PWM_HPM_L
PWM_HPM_R
PWM_HPP_L
PWM_HPP_R
PWM_M_1
PWM_M_2
B0034-02
PWM_M_3
PWM_M_4
PWM_M_5
PWM_M_6
PWM_M_7
PWM_M_8
7
PWM_P_1
(1) Type: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are 20-μA weak pullups and all pulldowns are 20-μA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups → logic-1 input; pulldowns → logic-0 input). Devices that drive
inputs with pullups must be able to sink 20 μA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 μA while maintaining a logic-1 drive level.
Copyright © 2013, Texas Instruments Incorporated
32
TAS5558
SLES273A – APRIL 2013 – REVISED JUNE 2013
2
Device Information
2.1
Physical Characteristics
2.1.1 TAS5558 Pin Assignments
DCA Package
(Top View)
PWM_HPM_L
1
56
PWM_P_6
PWM_HPP_L
2
55
PWM_M_6
PWM_HPM_R
PWM_P_5
3
54
PWM_HPP_R
4
53
PWM_M_5
VR_PWM
AVSS
5
52
PLL_FLTM
AVSS_PWM
6
51
PLL_FLTP
7
50
AVDD_PWM
VR_ANA
PWM_P_8
8
49
9
48
PWM_M_8
AVDD
ASEL_EMO2
10
47
PWM_P_7
PWM_M_7
MCLK
11
46
OSCRES
12
45
PWM_P_4
DVSS2_CORE
13
44
PWM_M_4
PWM_P_3
DVDD2_CORE
14
43
TAS5558
EMO1
15
42
PWM_M_3
PWM_P_2
RESET
16
41
HP_SEL
PWM_M_2
17
40
PDN
18
39
PWM_P_1
PWM_M_1
MUTE
19
38
SDA
20
37
VALID
SCL
21
36
DVSS1_CORE
LRCLK
DVDD1_CORE
22
35
SCLK
23
34
BKND_ERR
SDIN1
24
33
PSVC/MLCK
SDIN2
25
32
TEST
SDIN2_1
26
31
LRCLKO (LRCK_2)
SDIN2_2
27
30
SCLKO (SCLK_2)
VR_DIG
SDOUT (SDIN5)
28
29
P0113-02
Figure 2-1. TAS5558 Pinout
SLES273A – APRIL 2013 – REVISED JUNE 2013
5-V
TYPE
(1)
TERMINATION
(2)
DESCRIPTION
TOLERANT
NO.
10
DIO
Pullup
I2C Address Select. Address will 0X34/0X36 with the value of pin being "0' or
"1" during de-assertion of reset. Can be programmed to be an output (as energy
manager output for subwoofer)
9
P
Analog supply (3.3 V) for PLL.
50
P
3.3-V analog power supply for PWM. This terminal can be connected to the
same power source used to drive power terminal DVDD; but to achieve low PLL
jitter, this terminal should be bypassed to AVSS_PWM with a 0.1-μF low-ESR
capacitor.
5
P
Analog ground
4
Device Information
Copyright © 2013, Texas Instruments Incorporated
51
P
Analog ground for PWM. Must have direct return Cu path to analog 3.3V supply
Submit Documentation Feedback
for optimized performance.
Product Folder Links:
TAS5558
34
DI
Pullup
Active-low. A back-end error sequence is generated by applying logic low to this
terminal. The BKND_ERR results in no change to I2C parameters, with all H-
bridge drive signals going to a hard-mute state (Non PWM Switching).
35
P
3.3-V digital power supply. (It is recommended that decoupling capacitors of
0.1 μF and 10 μF be mounted close to this pin).
14
P
3.3-V digital power supply for PWM. (It is recommended that decoupling
capacitors of 0.1 μF and 10 μF be mounted close to this pin).
36
P
Digital ground 1
13
P
Digital ground 2
15
DO
Energy Manger Output interrupt - Asserted high when threshold is exceeded.
17
DI
5 V
Pullup
Headphone/speaker selector. When a logic low is applied, the headphone is
selected (speakers are off). When a logic high is applied, speakers are selected
(headphone is off).
22
DI
5 V
Pulldown
Serial-audio data left/right clock (sampling-rate clock)
31
DIO
5V
Pulldown
LRCLK for I2S OUT. Can also be used as LRCKIN_2 (I2S Input for SDIN2_x
and SRC Bank 2)
11
DI
3.3-V master clock input. The input frequency of this clock can range from 2
MHz to 50 MHz.
19
DI
5 V
Pullup
Soft mute of outputs, active-low (muted signal = a logic low, normal operation =
a logic high). The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
12
DO
1MΩ Resistor
Oscillator resistor (1% tolerance).
18
DI
5 V
Pullup
Power down, active-low. PDN powers down all logic and stops all clocks
whenever a logic low is applied. The I2C parameters are preserved through a
power-down cycle, as long as RESET is not active.
6
AIO
PLL negative filter.
7
AIO
PLL positive filter.
33
DO
Power-supply volume control PWM output or MCKO for external ADC (SDIN5
Source)
1
DO
PWM left-channel headphone (differential –)
3
DO
PWM right-channel headphone (differential –)
2
DO
PWM left-channel headphone (differential +)
4
DO
PWM right-channel headphone (differential +)
38
DO
PWM 1 output (differential –)
40
DO
PWM 2 output (differential –)
42
DO
PWM 3 output (differential –)
44
DO
PWM 4 output (differential –)
53
DO
PWM 5 output (lineout L) (differential –)
55
DO
PWM 6 output (lineout R) (differential –)
46
DO
PWM 7 output (differential –)
48
DO
PWM 8 output (differential –)
39
DO
PWM 1 output (differential +)
Submit Documentation Feedback
Product Folder Links:
TAS5558
www.ti.com
TAS5558
Device Information
5
Hide quick links:
Advertisement
Table of Contents
