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NJU72751A (MAIN: IC30)
NJU72751A
PIN CONFIGURATION
32
1
No.
Symbol
Function
1
V+
Power supply (+)
2
ADR0
Chip address setting terminal 0
3
InA1
Ach Input terminal 1
4
InB1
Bch Input terminal 1
5
NC
No connect
6
InA2
Ach Input terminal 2
7
InB2
Bch Input terminal 2
8
NC
No connect
9
NC
No connect
10
InA3
Ach Input terminal 3
11
InB3
Bch Input terminal 3
12
NC
No connect
13
InA4
Ach Input terminal 4
14
InB4
Bch Input terminal 4
15
REF
Digital block reference voltage terminal
16
DATA
Control data signal Input terminal
- 2 -
17
16
Symbol
Function
17
CLOCK
Clock signal Input terminal
18
NC
No connect
19
OutB4
Bch Output terminal 4
20
OutA4
Ach Output terminal 4
21
NC
No connect
22
OutB3
Bch Output terminal 3
23
OutA3
Ach Output terminal 3
24
REF_B
Bch Reference Voltage terminal
25
REF_A
Ach Reference Voltage terminal
26
OutB2
Bch Output terminal 2
27
OutA2
Ach Output terminal 2
28
NC
No connect
29
OutB1
Bch Output terminal 1
30
OutA1
Ach Output terminal 1
31
ADR1
Chip address setting terminal 1
32
V-
Power supply (-)
The TAS5142 is available in two thermally enhanced packages:
•
36-pin PSOP3 package (DKD)
•
44-pin HTSSOP PowerPad™ package (DDV)
Both package types contain a heat slug that is located on the top side of the device for convenient thermal
coupling to the heatsink.
TAS5142DKD (AMP: IC70)
GVDD_B
OTW
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
PWM_C
RESET_CD
PWM_D
GVDD_C
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TAS5142 Pin Discriptions
Terminal Functions
TERMINAL
NAME
DKD NO.
DDV NO.
AGND
9
11
BST_A
35
43
BST_B
28
34
BST_C
27
33
BST_D
20
24
GND
8
10
GND_A
32
38
GND_B
31
37
2
GND_C
24
30
GND_D
23
29
GVDD_A
36
44
GVDD_B
1
1
GVDD_C
18
22
GVDD_D
19
23
M1
13
15
M2
12
14
M3
11
13
NC
–
3, 4, 19, 20, 25,
42
OC_ADJ
7
9
OTW
2
2
OUT_A
33
39
OUT_B
30
36
OUT_C
25
31
OUT_D
22
28
PVDD_A
34
40, 41
PVDD_B
29
35
PVDD_C
26
32
PVDD_D
21
26, 27
PWM_A
4
6
PWM_B
6
8
PWM_C
14
16
PWM_D
16
18
RESET_AB
5
7
RESET_CD
15
17
SD
3
5
VDD
17
21
VREG
10
12
(1) I = input, O = output, P = power
31
DKD PACKAGE
DDV PACKAGE
(TOP VIEW)
(TOP VIEW)
GVDD_B
1
GVDD_A
1
36
OTW
2
BST_A
2
35
NC
3
SD
3
34
PVDD_A
NC
4
OUT_A
4
33
SD
5
GND_A
5
32
PWM_A
6
6
31
GND_B
RESET_AB
7
7
30
OUT_B
PWM_B
8
PVDD_B
8
29
OC_ADJ
9
BST_B
9
28
GND
10
10
27
BST_C
AGND
11
M3
11
26
PVDD_C
VREG
12
M2
OUT_C
12
25
M3
13
M1
GND_C
13
24
M2
14
14
23
GND_D
M1
15
15
22
OUT_D
PWM_C
16
PVDD_D
16
21
RESET_CD
17
VDD
17
20
BST_D
PWM_D
18
18
19
GVDD_D
NC
19
NC
20
P0018-01
VDD
21
GVDD_C
22
SLES126B – DECEMBER 2004 – REVISED MAY 2005
FUNCTION
(1)
DESCRIPTION
P
Analog ground
P
HS bootstrap supply (BST), external capacitor to OUT_A required
P
HS bootstrap supply (BST), external capacitor to OUT_B required
P
HS bootstrap supply (BST), external capacitor to OUT_C required
P
HS bootstrap supply (BST), external capacitor to OUT_D required
P
Ground
P
Power ground for half-bridge A
P
Power ground for half-bridge B
P
Power ground for half-bridge C
P
Power ground for half-bridge D
P
Gate-drive voltage supply requires 0.1-µF capacitor to AGND
P
Gate-drive voltage supply requires 0.1-µF capacitor to AGND
P
Gate-drive voltage supply requires 0.1-µF capacitor to AGND
P
Gate-drive voltage supply requires 0.1-µF capacitor to AGND
I
Mode selection pin
I
Mode selection pin
I
Mode selection pin
–
No connect. Pins may be grounded.
O
Analog overcurrent programming pin requires resistor to ground
O
Overtemperature warning signal, open-drain, active-low
O
Output, half-bridge A
O
Output, half-bridge B
O
Output, half-bridge C
O
Output, half-bridge D
P
Power supply input for half-bridge A requires close decoupling of
0.1-µF capacitor to GND_A.
P
Power supply input for half-bridge B requires close decoupling of
0.1-µF capacitor to GND_B.
P
Power supply input for half-bridge C requires close decoupling of
0.1-µF capacitor to GND_C.
P
Power supply input for half-bridge D requires close decoupling of
0.1-µF capacitor to GND_D.
I
Input signal for half-bridge A
I
Input signal for half-bridge B
I
Input signal for half-bridge C
I
Input signal for half-bridge D
I
Reset signal for half-bridge A and half-bridge B, active-low
I
Reset signal for half-bridge C and half-bridge D, active-low
O
Shutdown signal, open-drain, active-low
P
Power supply for digital voltage regulator requires 0.1-µF capacitor
to GND.
P
Digital regulator supply filter pin requires 0.1-µF capacitor to AGND.
GVDD_A
44
BST_A
43
42
NC
41
PVDD_A
PVDD_A
40
OUT_A
39
38
GND_A
37
GND_B
OUT_B
36
PVDD_B
35
34
BST_B
33
BST_C
PVDD_C
32
OUT_C
31
30
GND_C
29
GND_D
OUT_D
28
27
PVDD_D
TAS5142
26
PVDD_D
25
NC
BST_D
24
23
GVDD_D
P0016-02
5
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