Sharp HT-DV40H Service Manual page 97

Symbol Pin #
R_A19 86
R_A18 87
R_A17 88
R_A16 89
R_A15 91
R_A14 92
R_A13 93
R_A12 94
R_A11 95
R_A11 97
R_A11 98
R_A11 101
R_A11 102
R_A11 107
R_A11 108
R_A11 109
R_A11 110
R_A11 111
R_A11 113
R_A11 114
R_A11 115
R_A11 116
R_A11 117
R_A11 118
M_CS0_B/GPIO 120
M_BA0 121
M_DD[15] 122
M_DD[14] 123
M_DD[13] 124
M_DD[12] 126
M_DD[11] 127
M_DD[10] 128
M_DD[9] 129
M_DD[8] 130
M_A[11]/ GPIO 131
M_CLKO 133
M_CKE/GPIO 135
M_A[9] 136
M_A[8] 137
M_A[7] 138
Input/Output
Input/Output ROM / SRAM / flash address bus bit [19]
Priority selection
gpio_first[4][9] = 1
PINMUX_control[0][0] = 1
sft_cfg1[11:9] = 3'b110
sfg_cfg16[15:12] = 4'b1000
sfg_cfg18[3:0] = 4'b0001
sfg_cfg18[3:0] = 4'b0010
(other)
Input/Output ROM / SRAM / flash address bus bit [18]
Input/Output ROM / SRAM / flash address bus bit [17]
Input/Output ROM / SRAM / flash address bus bit [16]
Input/Output ROM / SRAM / flash address bus bit [15]
Input/Output ROM / SRAM / flash address bus bit [14]
Input/Output ROM / SRAM / flash address bus bit [13]
Input/Output ROM / SRAM / flash address bus bit [12]
Input/Output ROM / SRAM / flash address bus bit [11]
Input Clock input / crystal in (XTALI)
Output Clock output / crystal out (XTALO)
Input/Output USB bus D+ (only for USB versions)
Input/Output USB bus D- (only for USB versions)
Input/Output SDRAM data bus [7]
Input/Output SDRAM data bus [6]
Input/Output SDRAM data bus [5]
Input/Output SDRAM data bus [4]
Input/Output SDRAM data bus [3]
Input/Output SDRAM data bus [2]
Input/Output SDRAM data bus [1]
Input/Output SDRAM data bus [0]
Input/Output SDRAM write enable / row precharge
Input/Output SDRAM column address strobe
Input/Output SDRAM row address strobe / precharge
Input/Output SDRAM chip select 0, or GPIO[24]
Priority selection
sft_cfg0[0]=1íb1
gpio_first[1][8] = 1
(other)
Input/Output SDRAM bank select address [0]
Input/Output SDRAM data bus [15]
Input/Output SDRAM data bus [14]
Input/Output SDRAM data bus [13]
Input/Output SDRAM data bus [12]
Input/Output SDRAM data bus [11]
Input/Output SDRAM data bus [10]
Input/Output SDRAM data bus [9]
Input/Output SDRAM data bus [8]
Input/Output SDRAM address bus [11] or GPIO[25]
Priority selection
sft_cfg1[4]=1íb1
gpio_first[1][9] = 1
sft_cfg13[3:0] = 4'b1001
sft_cfg13[8:4] = 5'b01010
(other)
Output SDRAM clock output
Input/Output SDRAM clock enable, or GPIO[26]
Priority selection
sft_cfg0[1]=1íb1
(other)
Input/Output SDRAM address bus [9]
Input/Output SDRAM address bus [8]
Input/Output SDRAM address bus [7]
8 – 12
Description
Function
GPIO[73]
ROM_ADDR[19](default) Input/Output
NT1_11
FM_GPIOB[15]
FM_GPIOB[32]
FM_GPIOB[32]
GPIO[73]
Function
SDRAM chip select (default)
GPIO[24]
GPIO[24]
Function
SDRAM address bus M_A[11]
(default)
I GPIO[25]
IEC_RX
ADC_DATA
GPIO[25]
Function
DRAM clock enable (default)
GPIO[26]
HT-DV40H
Dir
Input/Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
Dir
Output
Input/Output
Input/Output
Dir
Output
Input/Output
Input
Input
Input/Output
Dir
Output
Input/Output