EUPA AP0 User Manual page 41

Ø
ECC / EC Option
ECC / EC Option:
- No ECC/EC
- ECC ON
- EC ON
Ø
Local In-Order-Queue Depth
Local In-Order-
Queue Depth:
- 1
- 2
- 4
- 8
Ø
DRAM Data Integrity Mode
DRAM Data
Integrity Mode:
- Disabled
- ECC
- Parity
Ø
ISA Line Buffer
ISA Line Buffer:
- Enabled
- Disabled
3-12
You could select the option of ECC (error-correcting
code) / EC (error checking) for memory.
You could select the depth of the Internal IOQ (In-
Order-Queue) buffer.
Select Parity or ECC (error-correcting code),
according to the type of installed DRAM.
The PCI to ISA Bridge has an 8-byte directional line
buffer for ISA or DMA bus master memory reads
from or writes to the PCI bus. When Enabled, an
ISA or DMA bus master can pre-fetch two double
words to the line buffer for a read cycle.
AP0
USER'S MANUAL