Panasonic PV-DV101 Manual page 287

VIDEO SIGNAL PROCESS II BLOCK DIAGRAM
MAIN C.B.A.
IC3201 (FORMATTING/EQUALIZER)
TO/FROM VIDEO I
80
DBR (0-3)
SIGNAL PROCESS
BLOCK DIAGRAM
83
(FROM IC6001(106))
RESET(L)
(FROM IC6001(63))
XWEH
FROM SYSTEM
(FROM IC6001(64))
CONTROL
XWEL
BLOCK DIAGRAM
(FROM IC6001(62))
XRE
(FROM IC6001(61))
ADDRESS STROBE
27MHz CLOCK
24.576MHz CLOCK
3
TO/FROM VIDEO I ADM (0-15)
SIGNAL PROCESS
BLOCK DIAGRAM
DBP (0-3)
MODULATOR
/DEMODULATOR
VITERBI EQUALIZER
ATF DET BPF
MICROCONTROLLER
INTERFACE
D/A CONVERTER
ADDRESS
RESET(L) RESET(L) XWEH XWEL XRE STROBE
52 54 55 57 58 61 64
30 4 78 77 74 75
66 68 70 73
IC5001 (HEAD AMP)
41 8
REC CLOCK 45 10
AGC
AGC CONTROL 27 3
DET
AGC
A/D CONVERTER AMP 8 6
AMP
A/D CONVERTER AMP 5 39
REC-C CONTROL 29 35
EQ HOLD 43 11
REC CONTROL 44 15
HEAD SW PULSE 2 38 16 LOGIC
HEAD SW PULSE 1 36 17
PB(H) 42 18
REC ON/OFF CONTROL 39 19
(FROM SAFETY TAB SW)
14
S-TAB ON(L)
20
27MHz
CLOCK
88
IC3202 (IEEE1394 INTERFACE)
73 XWEL
71 XRE
74 ADDRESS STROBE
94 27MHz CLOCK
28 24.576MHz CLOCK
50
51
53
56
58
61
63
66
68
69
75 DATA (4 BIT)
76
79
81
REC VIDEO SIGNAL PB VIDEO SIGNAL
LOGIC DRIVE GCA
CH1
HEAD
AMP
CH2
HEAD
1 43 AMP AMP
AMP
LPF
41
MICROCONTROLLER
INTERFACE
14
15
IEEE1394
INTERFACE
17
18
REC AUDIO SIGNAL PB AUDIO SIGNAL
CYLINDER UNIT
FP5
27
4
CH 1
26
FP5
HEAD
28
5
29
FP5
31
3 CH 2
30
HEAD
FP5
32
2
33
B2
ENVELOPE
20
B2 TO INTERFACE BOARD
HEAD SW
(FOR EVR ADJUSTMENT)
21 PULSE
B2
ATF
18
JACK C.B.A.
JK3703
DV JACK
FP6 FP3701
1 TPB(-)
7 9
FP6 FP3701
2 TPB(+)
8 8
FP6 FP3701
3 TPA(-)
5 11
FP6 FP3701
4 TPA(+)
6 10
5 GND