Panasonic PV-DV101 Manual page 285

CCD DRIVE BLOCK DIAGRAM
CCD C.B.A.
IC601 (CCD)
CCD Q601
PIN
IMAGE
8 BUFFER
14
SENSOR
PIN
4
5
PIN
3
4
PIN
2
3
PIN
1
2
PIN
13
7
1
PIN
10
10
PIN
11
9
PIN
12
8
MAIN C.B.A.
IC301 (CAMERA SIGNAL PROCESS)
DOUBLE
FP301
SAMPLING
30 MUX VGA
14
HOLD
CLAMP D/A CONVERTER
22 21 19 23 46 47 48
FP301
5
FP301
4
FP301
3
FP301
2
FP301
7
FP301
10
FP301
9
FP301
8
3
10BIT
CAMERA DATA (10 BIT)
A/D CONVERTER
12
CLAMP
20 16
IC304 (TIMING SIGNAL GENERATOR)
46 OB CLAMP PULSE
45 DUMMY CLAMP PULSE
R319 NOT USED
47 PRE BLANKING PULSE
38 SAMPLING PULSE 1
R332
39 SAMPLING PULSE 2
IC305 (CCD V-DRIVE)
LEVEL
7 19 V1 PULSE
CHANGE
5 DRIVE
LEVEL
8 16 CHARGE PULSE 1
CHANGE
LEVEL
3 9 20 V2 PULSE
CHANGE
LEVEL
14 21 V3 PULSE
CHANGE
17 DRIVE
LEVEL
13 15 CHARGE PULSE 2
CHANGE
LEVEL
18 12 22 V4 PULSE
CHANGE
LEVEL
1 10 23 SUB CONTROL PULSE
CHANGE
31 RESET PULSE
30 H1 PULSE
27 H2 PULSE
CAMERA DATA (0-9)
CAMERA DAC SERIAL CLOCK
CAMERA DAC SERIAL DATA
CAMERA DAC CS (L)
TO VIDEO SIGNAL PROCESS I
BLOCK DIAGRAM
A/D CLOCK 1 40
18MHz CLOCK 41 18MHz CLOCK
6MHz CLOCK 35 6MHz CLOCK
TG SERIAL CLOCK 9 TG SERIAL CLOCK
TG SERIAL DATA 10 TG SERIAL DATA
TG CS (L) 11 TG CS (L)
FCK 12 FCK (18MHz)
VD 3 VD
HD 4 HD
IC303
2FCK 8 1 6
3 4
X301
36MHz
OSC
REC VIDEO(CAMERA) SIGNAL