Table of Contents
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RDY/BSY
REG
BVD1
SDCENA
SDCD
SDWP
PCCENA
S
FD0
FD15
US
FA0
ADDRESS
BUS
FA19
IORD,FOE
CE1,CE2
CD1
CD2
PC CARD
I/F
126
IC6013
MCU(JPEG)
SD CARD
I/F
Y0
Y7
YC
C0
C7
OUT
GPIO
ENC RST
RXD
TXD
SYSIDO
DATA
MRESET
BUS
SDRAM
I/F
IC6015
DA,ENCODER
YD0
Y
YD7
CD0
C
CD7
RST
IC6001
AND GATE
IC6018
RESET
SYSRST
IC6018
128M SDRAM
TO DG10
JG3
Q6001,Q6008
Y
15
C
Q6003,Q6010
19
TXD
1
D3.3V
RXD
3
IDO
5
Q6005,Q6006
RST
9
TH-37PA30E/TH-42PA30E
JG-Board Block Diagram
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Table of Contents
