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SCHEMATIC DIAGRAM-14
+3.3D
IC203
TC74VHC138F
C220
(3 TO 8 DECODER)
0.1
16
VCC
W
1
A0
X
2
A1
Y
A2
3
4
CS2
Y
5
CS3
A
6
CS1
B
C
D
E
GND
F
G
8
H
R
S
U
V
T
I
J
K
L
IC215
M
TC7SZ32FU
N
(2 INPUT OR GATE)
O
P
GND
VCC
Q
W
1 2 3 4 5
X
Y
+3.3D
+3.3D
IC204
TC74VHC138F
C221
(3 TO 8 DECODER)
0.1
16
VCC
W
A0
1
X
A1
2
Y
3
A2
4
CS2
Y
5
CS3
CS1
6
GND
8
+5D
JP201
C222
0.1
23
VCC
V
1
21
U
44
20
T
43
19
S
18
2
7
7
H
R
3
17
6
9
G
Q
34
16
5
F
10
P
35
15
4
E
11
O
14
36
3
12
D
N
13
37
2
13
C
M
38
12
1
14
B
L
39
11
0
A
15
K
40
10
AD
J
9
41
I
8
42
H
4
7
G
5
6
F
6
5
E
4
7
3
D
8
C
9
2
B
10
1
A
11
0
VSS
13
IC205
QSIGX3C64004
(64M BIT MASK ROM)
R210
100
C223
0.1
23
VCC
V
21
1
U
20
44
T
43
19
S
2
18
7
H
7
R
3
17
6
G
9
Q
16
34
5
10
F
P
35
15
4
11
E
O
36
14
3
12
D
N
37
13
2
C
13
M
38
12
1
14
B
L
11
39
0
15
A
K
40
10
AD
J
41
9
I
42
8
H
4
7
G
6
5
F
6
5
E
7
4
D
8
3
C
2
9
B
1
10
A
11
0
VSS
13
IC206
QSIGX3C64005
(64M BIT MASK ROM)
A
33
BYTE
CE
12
V
U
OE
14
T
S
R
Q
15
31
P
P
14
O
O
29
13
N
N
27
12
25
M
M
11
22
L
L
10
20
K
K
9
J
J
18
8
I
I
16
DT
7
30
H
H
6
28
G
G
5
26
F
F
4
E
E
24
3
21
D
D
2
19
C
C
1
17
B
B
0
15
A
A
VSS
32
IC207
QSIGX3C64006
(64M BIT MASK ROM)
A
33
BYTE
CE
V
12
U
OE
14
T
S
R
Q
15
31
P
P
14
29
O
O
13
27
N
N
12
25
M
M
11
L
L
22
10
20
K
K
9
18
J
J
8
16
H
I
DT
7
30
I
H
6
G
G
28
5
26
F
F
4
24
E
E
3
21
D
D
2
C
C
19
1
B
B
17
0
15
A
A
VSS
32
IC208
QSIGX3C64007
(64M BIT MASK ROM)
B
C224
0.1
23
33
VCC
BYTE
1
21
CE
12
44
20
43
19
OE
14
18
2
3
17
34
16
35
15
15
31
P
14
14
O
36
29
13
13
N
37
27
38
12
12
25
M
39
11
11
22
L
40
10
AD
10
20
K
9
9
J
41
18
8
8
I
42
16
DT
4
7
7
30
H
5
6
6
28
G
6
5
5
26
F
4
4
E
7
24
8
3
3
21
D
9
2
2
19
C
10
1
1
17
B
11
0
0
15
A
VSS
VSS
13
32
C225
0.1
B
23
33
VCC
BYTE
21
CE
1
12
20
44
43
19
OE
14
2
18
3
17
16
34
15
35
15
31
P
36
14
14
29
O
37
13
13
27
N
38
12
12
25
M
11
11
L
39
22
40
10
AD
10
20
K
41
9
9
18
J
42
8
8
16
H
DT
4
7
7
30
I
6
6
G
5
28
6
5
5
26
F
7
4
4
24
E
8
3
3
21
D
2
2
C
9
19
1
1
B
10
17
11
0
0
15
A
VSS
VSS
13
32
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