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SCHEMATIC DIAGRAM-41
Q
MKB1 CIRCUIT
D1-D48
MA165TA5
R
MKB2 CIRCUIT
+5D
C2
0.1
C1
CN3
6.3V47
+5D
1
E
2
KB0
3
KB1
4
KB2
5
KB3
6
KB4
7
KF0
8
KS0
9
KF1
10
KS1
11
KF2
12
KS2
13
KF3
14
KS3
15
C5
C6
C7
E
16
47P
47P
47P
IC1 HD74LS138P
(3 TO 8 DECODER)
+5D
1
A0
6
9
A1
5
2
10
A2
4
3
11
4
CS2
Y
3
12
5
2
13
CS3
6
1
14
CS1
7 Y
0
7
15
GND
VCC
8
16
C3
0.1
D49-D96
MA165TA5
C8
C9
C10
47P
47P
47P
IC2 HD74LS138P
+5D
(3 TO 8 DECODER)
1
A0
6
9
2
A1
5
10
3
A2
4
11
CS2
Y
3
4
12
5
2
13
CS3
6
1
14
CS1
7
7 Y
0
15
8
GND
VCC
16
C4
0.1
CN1
1
2
3
4
5
6
7
CN2
1
2
3
4
5
6
7
8
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