Host Bridge/Controller (82443Bx) - HP P Class 450/500/550/600/650/700/750 Reference Manual

Host Bridge/Controller (82443BX)

Table 2-2. Host Bridge/Controller (82443BX)
Feature
Processor/Host Bus Support
• Optimized for Pentium® processor at: 100
MHz system bus frequency. Support for 66
MHz.
• Supports full Symmetric Multiprocessor
(SMP) Protocol for up to two processors; I/O
APIC related buffer management support
(WSC# signal).
• In-order transaction and dynamic deferred
transaction
support.
• Desktop optimized GTL+ bus driver
technology (gated GTL+ receivers for
reduced power).
Integrated DRAM Controller
• Up to 768 MB with registered DIMMs.
• 64-bit data interface with ECC support
(SDRAM only).
• Unbuffered and Registered SDRAM
(synchronous) DRAM support (x-1-1-1
access at 66 MHz, x-1-1-1 access at
100 MHz).
• Enhanced SDRAM Open Page Architecture
Support for 16 and 64-Mbit DRAM devices
with 2k, 4k and 8k page sizes.
Chapter 2
Feature
AGP Interface
• Supports single AGP-compliant device
(AGP-66/133 3.3V device).
• AGP Specifications Rev. 1.0 compliant.
• AGP-data/transaction flow optimized
arbitration mechanism.
• AGP side-band interface for efficient request
pipelining without interfering with the data
streams.
• AGP-specific data buffering.
• Supports concurrent CPU, AGP and PCI
Transactions ("expedite") support.
Power Management Functions
• Stop Clock Grant and Halt special cycle
translation (host to PCI bus).
• Mobile and "deep Green" Desktop supports
for system suspend/resume (i.e., DRAM and
power-on suspend).
• Dynamic power down of idle DRAM rows.
• SDRAM self-refresh power down support in
suspend mode.
• Independent, internal dynamic clock gating
reduces average power dissipation.
• Static STOP CLOCK support.
• Power-on Suspend mode.
• Suspend to DRAM.
• ACPI-compliant power management.
System Board
Chipset
37