HP P Class 450/500/550/600/650/700/750 Reference Manual page 107

Personal workstation
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Checkpoint Code
2Ah
2Ch
2Eh
2Fh
30h
32h
33h
36h
38h
3Ah
3Ch
3Dh
42h
45h
46h
48h
49h
4Ah
4Bh
4Ch
4Eh
50h
51h
52h
54h
Chapter 5
POST Routine Description
Clear 512 KB base RAM
RAM failure on address line xxxx*
RAM failure on data bits xxxx* of high byte of memory bus
Enable cache before system BIOS shadow
RAM failure on data bits xxxx* of high byte of memory bus
Test CPU bus-clock frequency
Initialize Phoenix Dispatch Manager
Warm start shutdown
Shadow system BIOS ROM
Autosize cache
Advanced configuration of chipset registers
Load alternate registers with CMOS values
Initialize interrupt vectors
POST device initialization
Check ROM copyright notice
Check video configuration against CMOS
Initialize PCI bus and devices
Initialize all video adapters in system
QuietBoot start (optional)
Shadow Video BIOS ROM
Display BIOS copyright notice
Display CPU type and speed
Initialize EISA board
Test keyboard
Set key click if enabled
Tests and Error Messages
Order in Which the Tests Are Performed
107

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