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EN 34
8.
TPM9.1AL LA
8.4
Diagram
10-1-17 B17, I2S Post amplifier & S/PDIF
Block diagram
BCLK
SDATA
Interface
LRCIN
Pinning information
2012-Jun-15
IC Data Sheets
2
I
C Control
Interface
Input
Audio Signal
Processing
VDDLA
1
N.C.
2
N.C.
3
N.C.
4
N.C.
5
PLL
6
MCLK
7
CLK_OUT
8
DGND
9
DVDD
10
DEF
11
SDATA
12
Figure 8-5 Internal block diagram and pin configuration
Out, AD82586 (IC U4104)
PLL
PLL
Internal
AD82586
System
Clock
PCM to PWM
SDM
36
35
34
33
32
31
AD82586
30
29
28
27
26
25
back to
div. table
Logic
Interface
Loudspeaker
Driver
VDDRA
N.C.
TEST_2
TEST_1
N.C.
N.C.
N.C.
SUB_SDATAO
LREX
DVDD
DGND
SDA
19330_304_120611.eps
ERROR
L
R
120612
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