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This user's guide describes the characteristics, operation, and use of the TPS65735EVM-703 evaluation
module (EVM). The TPS65735EVM-703 is a fully assembled and tested platform for evaluating the
performance of the TPS65735 single-chip power management device. This document includes schematic
diagrams, a printed circuit board (PCB) layout, bill of materials, and test data. Throughout this document,
the abbreviations EVM, TPS65735EVM, and the term evaluation module are synonymous with the
TPS65735EVM-703 unless otherwise noted.
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Schematic
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H-Bridge Operation : Ch. 1 - Function Generator Input to HBR1, Ch. 2 - LCRP output, Ch. 3 - Function
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H-Bridge Operation : Ch. 1 - Function Generator Input to HBL1, Ch. 2 - LCLP output, Ch. 3 - Function
SLVU418 - June 2011
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TPS65735 System Evaluation Board
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Copyright © 2011, Texas Instruments Incorporated
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TPS65735 System Evaluation Board
User's Guide
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Table of Contents
Related Manuals for Texas Instruments TPS65735EVM-703
Summary of Contents for Texas Instruments TPS65735EVM-703
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Page 1: Table Of Contents
TPS65735 System Evaluation Board This user’s guide describes the characteristics, operation, and use of the TPS65735EVM-703 evaluation module (EVM). The TPS65735EVM-703 is a fully assembled and tested platform for evaluating the performance of the TPS65735 single-chip power management device. This document includes schematic diagrams, a printed circuit board (PCB) layout, bill of materials, and test data. - Page 2 Thermal Performance – Bottom Side ....................Top Assembly – Silkscreen ........................Top Layer ....................... Bottom Layer List of Tables ......................Bill of Materials ....................... Evaluation Materials SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
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Page 3: Introduction
Input Voltage Low VIL (BST_EN, CHG_EN, SW_SEL, VLDO, HBRx, HBLx) 0.4 V Input Voltage High VIH (BST_EN, CHG_EN, SW_SEL, VLDO, HBRx, HBLx) 1.2 V SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... -
Page 4: Schematic
Schematic www.ti.com Schematic Figure 1. Schematic SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... -
Page 5: Connector And Test Point Descriptions
J12 pin 1 is GND, pin 2 is the TS pin of the TPS65735. This header, J12, is to connect an external thermistor to the TPS65735 and should be left floating if not used. SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... -
Page 6: Jumpers
Verify JP1 is set with S1 and SWITCH shorted, press the push-button (S1) and verify with voltmeter that the output voltage is 10V ± 1 V. SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... -
Page 7: Tps65735Evm Test Data
Operation Waveforms Figure 2. Boost Output Ripple : Vbat = 3.2 V and 1 mA Load on Boost SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... -
Page 8: Startup : Vin = 5 V, 1 Ma Load On Boost, And 15 Ma Load On Ldo
Figure 3. Startup : Vin = 5 V, 1 mA Load on Boost, and 15 mA Load on LDO Figure 4. Shutdown : Vin = 5 V, 1 mA Load on Boost, and 15 mA Load on LDO SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... -
Page 9: Startup : Vbat = 3.6 V, 1 Ma Load On Boost, And 15 Ma Load On Ldo
Figure 5. Startup : Vbat = 3.6 V, 1 mA Load on Boost, and 15 mA Load on LDO Figure 6. Shutdown : Vbat = 3.6 V, 1 mA Load on Boost, and 15 mA Load on LDO SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... -
Page 10: Switchnode : Vbat = 3.6 V, No Load, 0.5Μs/Div
Figure 7. Switchnode : Vbat = 3.6 V, No Load, 0.5µs/div Figure 8. Switchnode : Vbat = 3.6 V, No Load, 10 µs/div SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... -
Page 11: Load Transient, Boost : Vbat = 3.6 V With 0 Ma To 5 Ma Transient, Constant 15 Ma Load On Ldo. Ch3 Bstout Ch4 Iboost
Figure 10. Load Transient, Boost : Vbat = 3.6 V with 5 mA to 0mA Transient, Constant 15 mA Load on LDO. CH3 Bstout CH4 IBOOST SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... -
Page 12: Load Transient, Ldo : Vbat = 3.6 V With 0 Ma To 30 Ma Transient. Ch3 Vldo, Ch4 Ivldo
CH3 VLDO, CH4 IVLDO Figure 12. Load Transient, LDO : Vbat = 3.6 V with 30 mA to 0 mA Transient. CH3 VLDO, CH4 IVLDO SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... -
Page 13: Bridge Operation : Ch. 1 - Function Generator Input To Hbr1, Ch. 2 - Lcrp Output, Ch. 3 - Function Generator Input To Hbr2, Ch. 4 - Lcrn Output
Figure 14. H-Bridge Operation : Ch. 1 - Function Generator Input to HBL1, Ch. 2 - LCLP output, Ch. 3 - Function Generator Input to HBL2, Ch. 4 - LCLN output SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... -
Page 14: Measured Data
Thermal Performance Figure 16 Figure 17 show the typical thermal performance for the TPS826xx for both the top side and the bottom side, respectively SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... - Page 15 TPS65735EVM Test Data www.ti.com 6.3.1 Top Side Figure 16. Thermal Performance – Top Side 6.3.2 Bottom Side Figure 17. Thermal Performance – Bottom Side SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
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Page 16: Evm Assembly Drawings And Layout
EVM Assembly Drawings and Layout www.ti.com EVM Assembly Drawings and Layout Figure 18. Top Assembly – Silkscreen Figure 19. Top Layer SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... - Page 17 EVM Assembly Drawings and Layout www.ti.com Figure 20. Bottom Layer SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated...
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Page 18: Bill Of Materials
0603 NCP18W103J03RC Murata TP1, TP2 Test Point, O.032 Hole — Shunt, 100-mil, Black 0.100 929950-00 — PCB, 1.84" x 1.65" x 0.031" HPA703 SLVU418 – June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated... - Page 19 Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
- Page 20 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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