VIA Mainboard 845G Series Manual page 31

Managing The PC BIOS
%   +#!  !
+ C  1, &  &&'/
9)
  !
  , 

&)
 ,"
 

), 

' , !
  "

9)
9)J

&)J
  "

9)
9)J
' , !

"
/ C( ,"
/

" 
;$4
& , 


@  
;$4
& , 

"

)
 5

  " 
  , 

  "
' 

  

)*'
)- (
 D
+ ;.



KK
4 5& -
@*)
  !
KK

4 5& -
@*)

4 5& -
/ 
;(%% 
 D

(


;
 - "

DRAM Timing Selectable
This field determines the DRAM read/write timing. The performance parame-
ters of the memory chips (DRAM) you have installed will determine the value
in this field. Do not change the value from the factory setting unless you install
new memory that has a different performance rating than the original DRAMs.
CAS Latency Time
The time delay (in clock cycles, CLKS) that passes before the SDRAM starts to
carry out a read command after it has been received. The number of CLKs that
occur before the first part of a burst transfer is completed is also determined
by this field.
DRAM RAS# to CAS# Delay
When the DRAM is refreshed, both rows and columns are addressed sepa-
rately. This setup allows you to determine the timing of the transition from
Row Address Strobe (RAS) to Column Address Strobe (CAS).
The 845G MAINBOARD Series


   +'%$ %

F;"
'G

FG

FG

FG

FG

F)(G

F  G

F   G

F   G

F  G

F
G

F G





F  G

F8 ;G

F   G

F)(G

$ 
-

(
 
!

Page 31