Supermicro SC836B JBOD Series User Manual page 85

B-6 JBOD Control Board
In a cascaded configuration, the first chassis (head node) includes a motherboard
and at least one host bus adapter (HBA). Other storage enclosures in the system
must be equipped with a JBOD control board. This board controls power and
provides some mangement over the chassis components. For more information,
see Appendix C in this manual, or the Supermicro web site at www.supermicro.com.
The SC836B JBOD chassis includes the JBOD control board.
MH1
S_ICE_HDR
J37
2 20
EC16
CG3 CG1
SEC_J3
19
1
L12
CG2
CG1
SEC_J2 CG3
CG2
MH2
EC15
CG3 CG1
BAR CODE
SEC_J1
CG2
CG3 CG1
EC13 EC14
SEC_J0
CG2
S_HB_LED
S_SDB
A C
J36 4
1
J35
4
S_UART 1
26 25 20 15
4
H E A
H E A
1
4 1 PWR3
PWR4
1 1
2
5 5
J29
MH3
U48
9
1
S_MDIO
1 2 3
SMB
MH13
EC19 EC20
L10
L7
2 4
SMB
1 3
A
J17
C
SECONDARY EXPANDER
2 4
EC17 1
1
3
PRI_I2C1
WWN
HS1
AF
AE
Y
R
K
Y2 PWR2
E
A
10 5 1
1
PWR1
10
1
J34
S_JTAG
MH12
1
JP1 to JP4 (see Appendix C)
4
MH1
1 3
2
4
1 6
1 C146
3 4
2
4
9 JP2
JP3
1 3
2 4
5
FAN9
1 3
2
J3 4
JP7
#
+ 3
1
U9
Y1
BT1
J2
LE1
U13 U14
17 16 15 19 F1 JP6
6 12 C115
U7
48 37
L7 36
12
25
13
24
MH4
18
1
14 13 7
J8
Figure 3EL-11. SAS I
Appendix B Backplane Specifications
MH5
P_SDB
ACTLED1 1 J24 4 1 J19 P_UART P_HB_LED
D21
1 4
A
C
EC1 EC2
EC3 EC4 J28
2 20
P_ICE_HDR
MH7
L6 1 C21
26
25
EC12
EC11
20
U1
15
10
H E A
H E A
5
1 1
LT3
5 5
4 1
A
U8
P_MDIO 2 8
9
MH9
J27
1
4
J18
1
P_JTAG
BPN-SAS3-836EL backplane
4
4 4 4 4
4
FAN2 FAN3 FAN4 C160 FAN5 FAN6
+
U*
Q18
15
10
Q13
U17 U18 U16
5
1
A E K R Y
J4 J5 J6 J7
2 2 2 2
1 1
1
1
7 7 7 JP5
1
8 8 8 8 7 1-2:SAS3
2-3:SAS2_847D JP5 3 20 JF1
CB3 JBOD Control Board
C Cabling
2
B-13
MH6
L2
A C A C
5V_LED1
L4 12V_LED1
BPN-SAS3-836EL2
EC10 EC9
REV 1.01
DESIGNED IN USA
L5
L3
PRI_J3
P_MDIO
EC7 EC8
WWN
PRI_J2
MH11
HS2
PRI_J1
LT4
E K R Y AE AF
PRI_J0
EC6 EC5
L1
Y1
10
4
MH2
1
5
13
+
C
C10
U1 C4
FAN10
A
U5
C89
C9
+
9 7 3 1
+
U6
C8
JPW1
24
JF1
2 MH3 NMI X PWR LED X NIC1 X OH/FF X RST ON PWR ON
12
MH4
1 2 3
CG3 CG1
CG2
CG3
CG1
MH8
CG2
CG3 CG1
CG2
CG1
CG3
CG2
MH10