Linear Technology DC1717A Demo Manual page 3

operating principles
The other driving mode of the P-channel MOSFETs is used
in the voltage switching operation, when the higher priority
rail replaces the rail losing validity. The gate driver oper-
ates with a fixed current, which is defined by the external
component parameters R
The LTC4417 circuit designer should select the value of
R and C based on the MOSFET parameters, power rail
S S
source characteristics, acceptable output voltage droop
during transient, and the value of load capacitance.
Design proceDure for moDification of Dc1717a
The valid input range for any supply is controlled by the
OV and UV comparators with resistive dividers (R4-R13).
See the LTC4417 data sheet for design equations to select
resistors to match a particular requirement.
Dual MOSFETs, Q1-Q3, may be replaced with single devices
Q4-Q9 by simply removing Q1-Q3. Pads for Q4-Q9 are
located on the bottom side of the board.
The requirement for AVI may be eliminated by removing
jumpers JP2 and JP3, and removing resistor R19. This
modification leaves the LEDs unpowered and the inputs
of U2 and U3 clamp the VALID pins at 0.7V, but otherwise
leaves the LTC4417 operating autonomously.
The following design considerations and equations dem-
onstrate the interrelation of the main component values
and transient parameters in the rail transitions, when the
output voltage exceeds 0.7V. The variables C
used in the design equations correspond to the following
board components:
• C20, R23 for V1 (+12V channel)
• C21, R26 for V2 (+5.0V channel)
• C22, R28 for V3 (+8.0V channel)
To have dominant influence on the transient time C
be at least ten times larger than the P-channel MOSFET's
reverse transfer capacitance (Miller). In this design, for
all rails, C (C20, C21,and C22) equals 47nF.
S
and C shown in Figure 1.
S S
and R
S
should
S
DEMO MANUAL DC1717A
V1
12V WALL
+
ADAPTER
C
IN1
68µF
The slew rate of the output voltage can be expressed as
a function of C :
S
dV dV
OUT CS
= =
dt dt
where:
• V is the LTC4417 parameter rated in the data sheet
SINK
as ∆V = 4.5V-6V.
G(SINK)
• V is the P-channel gate threshold voltage, which
THRES
is between –1.5V and –3.5V for the Si7905DN installed
on the board.
• R = 249Ω and C
S
Given that dV /dt is based on the transient time require-
OUT
ment, it is possible to define R
The output voltage slew rate, dV
S
with the listed parameters is between 85V/ms and 385V/ms.
During the transition of rails, the load can be disconnected
from any rail for a time:
T = t
DISCON G(SWITCHOVER)
Two first summands of the T
data sheet as:
t = (0.3 to 3)µs
G(SWITCHOVER)
t = (5 to 13)µs
pVALID(OFF)
IRF7324
M1 M2
C
S
D
C S
R
VS1
S
BAT54
VS1 G1
V
OUT +
LTC4417
Figure 1
V – | V |
SINK THRES
R • C
S S
= 47nF.
S
from equation 1.
S
/dt, range for the circuit
OUT
+ t + t
pVALID(OFF) GATE_THRES
are rated in the LTC4417
DISCON
V
OUT
C
L
47µF
(1)
dc1717afa
3