Table of Contents
Advertisement
Connector JP3 Orientation
SPEAKER
RST_SW
HD_LED
CN25: External Reset Button
PIN Description
1
2
3.19 Watchdog Timer
There are three access cycles of Watch-Dog Timer as Enable, Refresh
and Disable. The Enable cycle proceeds via READ PORT 443H
whereas the Disable cycle proceeds via READ PORT 045H. A
continued Enable cycle after a first Enable cycle means Refresh.
Once the Enable cycle is active, a Refresh cycle is requested before
the time-out period. This restarts counting of the WDT period. When
the time counting goes over the preset period of WDT, it will assume
that the program operation is abnormal. A System Reset signal to
re-start or a NMI cycle to the CPU transpires when such error happens.
Jumper JP1 is used to select the function of Watchdog Timer.
JP1: Watchdog Timer Active Type Setting
Options
Active NMI
System Reset
Disabled WDT (default)
22
1
2
PWR LED
3
4
5
6
EXT_SMI
7
8
9
10
PWR button
11
12
13
14
SLP button
15
16
Reset
1
GND
Settings
1
Short 1-2
Short 2-3
Open
2
3
Advertisement
Table of Contents
