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JP33: System Front Panel Connector
PIN Description
1
3
5
7
9
11
Reset Switch
13
330Ω Pull +5V
15
HDD LED
Connector JP33 Orientation
SPEAKER
RST_SW
HD_LED
3.18 Watchdog Timer
There are three access cycles of Watchdog Timer as Enable, Refresh
and Disable. The Enable cycle proceeds via READ PORT 443H
whereas the Disable cycle proceeds via READ PORT 045H. A
continued Enable cycle after a first Enable cycle means Refresh.
Once the Enable cycle is active, a Refresh cycle is requested before
the time-out period. This restarts counting of the WDT period. When
the time counting goes over the preset period of WDT, it will assume
that the program operation is abnormal. A System Reset signal to
re-start or a NMI cycle to the CPU transpires when such error happens.
Jumper JP31 is used to select the function of Watchdog Timer.
JP31: Watchdog Timer Active Type Setting
Options
Active NMI
System Reset
Disabled WDT (default)
22
PIN
Description
+5V
2
330Ω Pull +5V
GND
4
N/C
6
Speaker
8
GND
10
12
14
16
1
2
PWR LED
3
4
5
6
EXT_SMI
7
8
9
10
PWR button
11
12
13
14
SLP button
15
16
Settings
Short 1-2
Short 2-3
Open
GND
EXT SMI
GND
PW Button
GND
SLP Button
GND
1
3
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