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• MAIN BOARD (1/2) IC901 ES3210 (MPEG AUDIO/VIDEO DECODER)
Pin No.
Pin Name
1
VCC
2
DRAS B
3
DWE B
4
MA0
5
MA1
6
MA2
7
MA3
8
MA4
9
MA5
10
MA6
11
MA7
12
MA8
13
DBUS0
14
DBUS1
15
DBUS2
16
DBUS3
17
DBUS4
18
DBUS5
19
DBUS6
20
DBUS7
21
DBUS8
22
DBUS9
23
DBUS10
24
DBUS11
25
DBUS12
26
DBUS13
27
DBUS14
28
DBUS15
29
RESET B
30
VSS
31
VCC
32
YUV0
33
YUV1
34
YUV2
35
YUV3
36
YUV4
37
YUV5
38
YUV6
39
YUV7
40
VSSCN B
41
HSSCN B
42
CLK
43
PCLK2XSCN
44
PCKLQSCN
45
AUX0
I/O
—
Power supply terminal (+3.3V)
O
Row address strobe signal output to the D-RAM (IC903) "L" active
O
Write enable signal output to the D-RAM (IC903) "L" active
O
O
O
O
O
Address signal output to the D-RAM (IC903)
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Two-way data bus with the D-RAM (IC903)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Reset signal input from the system controller (IC701)
—
Ground terminal
—
Power supply terminal (+3.3V)
O
O
O
O
Video data output to the video encoder (IC920)
(YUV; Y: luminance signal, UV: Screen video interface chrominance data bus)
O
O
O
O
O
Vertical synchronous signal output to the video encoder (IC920)
O
Horizontal synchronous signal output to the video encoder (IC920)
I
System clock signal input terminal Not used (open)
I
System clock signal (27 MHz) input from the video encoder (IC920)
O
Pixel clock qualifier output for the screen video interface Not used (open)
O
Sub control signal output terminal Not used (open)
Function
– 29 –
"L": reset
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